On my board the problem is caused by the line DRAM_REG[44] = 0x01020202; in the DDR2 133MHz definition in emi_settings.c
The value of 01 breaks the tWTR minimum timing requirement of 2 clocks or 7.5ns whichever is greater in the Micron datasheet for the DDR2 part I use.
Changing the value to 0x02020202 works for me.
Hope this helps some-one.
Clock switching saves 20% power for me and is well worth a look for idle periods.
Matt