iMX28 FEC MDC clock rate

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iMX28 FEC MDC clock rate

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Contributor II

Hello,

I'm using the linux-2.6.35.3 SDK and notice in drivers/net/fec.c function fec_enet_mii_init

    fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk), 5000000) << 1;

#ifdef CONFIG_ARCH_MXS

    /* Can't get phy(8720) ID when set to 2.5M on MX28, lower it*/

    fep->phy_speed <<= 2;

#endif

    writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);

This is incorrect for the iMX28 as the MDC clock rate is determined by the 151MHz bus clock and not the 50MHz fep->clk.  See page 1668 of the reference manual.  This was probably the reason why phy(8720) didn't respond until the calculated rate was divided by 4.

I've used

#ifndef CONFIG_ARCH_MXS

    /*

     * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)

     */

    fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk), 5000000) << 1;

#else

    /*

     * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * (MII_SPEED + 1))

     */

    fep->phy_speed = (DIV_ROUND_UP(clk_get_rate(clk_get(&pdev->dev, "h")), 5000000)-1) << 1;

#endif

    writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);

I now have a 2.44MHz clock rather than the original 1.84MHz clock.

There is a similar mistake in fec_switch.c but I'm not using that.

Matt.

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Senior Contributor II

Hi Matt,

I have verified on ENET_MDC signal, with your changes, the MDC frequency is 2.445MHz which is closed to 151578666/31. fec_enet_mii_init() in drivers/net/fec.c and drivers/net/fec_switch.c are need to be corrected. I will push the changes into our git.

Thanks for your works on this defect!

Jacky

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Senior Contributor II

Are you working on iMX28 EVK board?

With you changes and I probed on R171 on EVK which is the ENET_CLK signal, I always got 50MHz either the eth0 port has connected to 10MHz Hub or 100MHz switch.

Jacky

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Contributor II

Hi Jacky,

The ENET_CLK is not the right clock.  The MDC clock that forms part of the MDC & MDIO MII management interface is on R138 and is called ENET_MDC.

ENET_CLK should be 50MHz for RMII operation.

ENET_MDC is normally set at 2.5MHz although many PHYs will operate at a faster rate.

ENET_MDC is not related to ENET_CLK as the code assumes but is related to an internal bus clock (clkp or clkh) which is 151MHz on my board.  This is stated on p1668 of the reference manual.

I am not using the EVK but my own board which is similar in many ways.

Best Regards,

  Matt.

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Senior Contributor II

Hi Matt,

I have verified on ENET_MDC signal, with your changes, the MDC frequency is 2.445MHz which is closed to 151578666/31. fec_enet_mii_init() in drivers/net/fec.c and drivers/net/fec_switch.c are need to be corrected. I will push the changes into our git.

Thanks for your works on this defect!

Jacky

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Senior Contributor II

I'm studying the code which is quite confusing. I will get back to you later.

Regards,

Jacky

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