iMX28 Boot Failures with Caches Enabled

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iMX28 Boot Failures with Caches Enabled

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markwilliams
Senior Contributor I

Hi,

We have had reports from our sub contract manufacturer of boards failing to program using mfgtool. Actually the boards are failing during boot of the WinCE UUT image (the one used by mfgtool to transfer the actual OS/eboot). A recent batch of 200 boards, 25 failed. Replacing the processor they were fine.

I have had some boards back for analysis and found they fail shortly after OEMInit in the early kernel start - the boot just hangs. After a lot of debugging and trying different things I found that if I disable the caches (OEMARMCacheMode returns 0x00 rather than 0x0C) then the failing boards then boot fine. Re-enabling caches they fail at the same point.

I have ran DDR test and my own test over the whole RAM and this is fine.


I thought that these boards may have something in their RAM, perhaps left by the boot ROM uninitialised. Or perhaps an issue with the fact the MMU was set up for D-caching for hab boot then reconfigured during WinCE startup. So I tried disabling the MMU for the boot ROM using the relevant fuse. This made no difference - for the failing boards having D-Cache enabled in the UUT image they would fail to boot once transferred over USB.

I am still looking into what this could be but it is odd that it is only a small quantity of boards - usually I would point that at an assembly defect but there is no evidence of this so far. I am trying to understand why they only fail with cache enabled.

Thanks,

Mark

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Mark

for d-cache one can consider ENGR119653 USB: ARM to USB register error issue

Chip Errata for the i.MX28

For ddr memory one can try to tweak drive strength, If heating up the part causes more

failures, then the drive strength is too low and the signals may not rise/fall fast enough.

Best regards
igor
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markwilliams
Senior Contributor I

Hi Igor,

Thanks for the reply. We have been working with the imx28 for the last 8 years and produced around 20,000 of these boards so far. Qualified over temperature range with ddr stress testing. The failures are recent.

I have studied the errata many times over the years when dealing with issues. At the point of failure boot rom has loaded the image to ram and is running it. The image is not using usb at this point (shortly after wce boot has set up caches) but i have work arounds for that errata in the usb driver.

For the same board if i have cache enabled it hangs. If i disable cache it boots into windows ce.

My thoughts are the way windows ce starts and enables the cache. It then performs a few functions before flushing the cache.

However it just seems to set up the mmu for the cached range. Surely at this point the caches may contain random data? Is the cache cleared on reset? I tried disabling rom mmu use so nothing left in cache from rom code when handing to wce boot.

Mark

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Mark

in general this may be also quality issue and failed parts can be sent

to FA procedure, details can be obtained in local marketing office.

Best regards
igor

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