iMX253 using MII interface

[gregungerer]

Hi All,

I am working with a new custom board based around the iMX253. For the most part it is working. Booting up from SPI flash with u-boot and linux (3.8) all running fine.

The board is wired with a Realtek 8201 PHY hanging of the FEC module. So it is wired in full MII mode. Now it mostly works. u-boot can network load, and under linux the interface works. But it is occasionally losing packats - from both u-boot and linux. Quite noticeable when u-boot has to retry while tftp loading. Flood pinging from linux shows a loss rate of around 1 to 2 packets a second.

Looking at the FEC lines from the iMX253 to the 8201 PHY on an oscilloscope both RDATA0 and RDATA1 look pretty good, but RDATA2 and RDATA3 don't look anywhere near as good - they look a little runty and don't push up anywhere near 3.3v. Thinking this might be the source of my packet loss.

I have played around with the PAD/pin settings but nothing seems to improve the signal quality on those lines.

Does anyone else have experience using something like the iMX253 in full MII mode to a PHY?

Any tricks to getting it working right?

Regards

Greg

[gregungerer]

Hi Fabio,

[ My direct reply-all emails are bouncing back to me, marked as failed. They seem to show up here in the forum with just the single line. Posting this response direct into the web interface.]

On 25/04/13 08:58, Fabio Estevam wrote:

Let's check the IOMUX setup for the pins RDATA2 and RDATA3 in your case.

Please let us know which pads you use for RDATA2/3.

We have those mapped to pads A20 and A21.

All the extra MII signals (above those of RMII) are mapped on pads A17
through A25.

For example: if you use pad IOMUXC_SW_MUX_CTL_PAD_LD11 as RDATA2, then
you need to set the MUX MODE as alt mode 5, according to the reference
manual:

101: Select mux mode: ALT5 mux port: RDATA[2] of instance: fec.

Yep. I have those RDATA2/3 pins muxed using ALT7 (so IOMUX register
offsets 0x1c through 0x3c set to 0x7).

One very important thing is that some mx25 pins require an additional
setting of the select_input registers. In this example, we do need to
configure it as the manual states:

NOTE: Pad LD11 is involved in Daisy Chain.

- Config Register IOMUXC_ESDHC2_IPP_DAT1_IN_SELECT_INPUT for mode ALT6.

- Config Register IOMUXC_FEC_FEC_RDATA_2_SELECT_INPUT for mode ALT5.

So you need to setup the IOMUXC_FEC_FEC_RDATA_2_SELECT_INPUT correctly.

Yeah, I saw those too. I set those to 0 - which looks to be the correct
setting in this case from the daisy chain list in the reference manual.

It is certainly the case if I set these input select registers to
anything other than 0 then the ethernet stops working completely.
(As you would expect).

This is a 2-bit register:

Selecting Pads Involved in Daisy Chain.

Instance: fec, In Pin: fec_rdata[2]

00: Selecting Pad: A20 for Mode: ALT7.
01: Selecting Pad: LD11 for Mode: ALT5.
10: Selecting Pad: SD1_CMD for Mode: ALT2.

as we want ALT5, then we need to write 01 to the register
IOMUXC_FEC_FEC_RDATA_2_SELECT_INPUT

Hope this example helps.

It does, thanks.

In talking this issue over with my board designer he is concerned that
the the extra FEC MII pins on pads A17 through A25 may be driven by
the RAM/bus power plane. Given we are using DDR with 1.8V signaling
he thinks these pads may be driven/clamped to that 1.8V. Do you know if
this is the case?

Regards
Greg

[YixingKong · Accepted solution]

Greg,

SOmething further:

Q: Is the MX25 capable of this?

A: Yes,  NVCC_EMI1/2 can be at different voltages.

Q: What other pads are on the NVCC_EMI1 rail of the device?

A:  Need some more time to check with owner

--------------------------------------

please click Correct ANswer/Helpful Answer if yur question is answered.

Thanks,

Yixing

[simon01]

Hi,

I have a similar problem to this but with an mx53. Did you resolve the issue?

Thanks

Simon

[gregungerer]

Hi Simon,

In the end we switched to using an RMII interface PHY instead. We couldn't see any way to have 1.8V DDR RAM and use the full PHY interface.

This actually caught us out on one of the SPI interfaces as well on this first prototype.

Careful redesign taking into consideration what power plain powers what mux pins worked out. We have a second round prototype up and running and it is all working as expected now.

Regards

Greg

[YixingKong]

As checked with design, power rail for NVCC_EMI1/2 are listed as below:

left_000_cs4(    .ovdd(NVCC_EMI1),

left_001_cs5(    .ovdd(NVCC_EMI1),

left_002_cs1(    .ovdd(NVCC_EMI1),

up_036_sd5(    .ovdd(NVCC_EMI1),

up_037_sd2(    .ovdd(NVCC_EMI1),

up_039_sd3(    .ovdd(NVCC_EMI1),

up_040_sd4(    .ovdd(NVCC_EMI1),

up_042_sd0(    .ovdd(NVCC_EMI1),

up_043_sd1(    .ovdd(NVCC_EMI1),

up_045_sd7(    .ovdd(NVCC_EMI1),

up_046_dqm0(    .ovdd(NVCC_EMI1),

up_048_sd6(    .ovdd(NVCC_EMI1),

up_049_sd13(    .ovdd(NVCC_EMI1),

up_051_sd10(    .ovdd(NVCC_EMI1),

up_052_sd11(    .ovdd(NVCC_EMI1),

up_054_sd12(    .ovdd(NVCC_EMI1),

up_055_sd8(    .ovdd(NVCC_EMI1),

up_056_sd9(    .ovdd(NVCC_EMI1),

up_058_sd15(    .ovdd(NVCC_EMI1),

up_059_dqm1(    .ovdd(NVCC_EMI1),

up_060_sd14(    .ovdd(NVCC_EMI1),

up_062_bclk(    .ovdd(NVCC_EMI1),

up_063_a25(    .ovdd(NVCC_EMI1),

up_064_a24(    .ovdd(NVCC_EMI1),

up_066_a23(    .ovdd(NVCC_EMI1),

up_067_a22(    .ovdd(NVCC_EMI1),

up_068_a21(    .ovdd(NVCC_EMI1),

up_070_a20(    .ovdd(NVCC_EMI1),

up_071_a19(    .ovdd(NVCC_EMI1),

up_072_a18(    .ovdd(NVCC_EMI1),

up_074_a17(    .ovdd(NVCC_EMI1),

up_075_a16(    .ovdd(NVCC_EMI1),

up_077_a15(    .ovdd(NVCC_EMI1),

up_078_a14(    .ovdd(NVCC_EMI1),

up_080_a10(    .ovdd(NVCC_EMI1),

up_081_oe(    .ovdd(NVCC_EMI1),

up_083_eb1(    .ovdd(NVCC_EMI1),

up_084_eb0(    .ovdd(NVCC_EMI1),

up_086_rw(    .ovdd(NVCC_EMI1),

up_087_ecb(    .ovdd(NVCC_EMI1),

up_089_lba(    .ovdd(NVCC_EMI1),

up_090_cs0(    .ovdd(NVCC_EMI1),

right_076_a13(    .ovdd(NVCC_EMI2),

right_077_a12(    .ovdd(NVCC_EMI2),

right_078_a8(    .ovdd(NVCC_EMI2),

right_079_a11(    .ovdd(NVCC_EMI2),

up_000_a9(    .ovdd(NVCC_EMI2),

up_001_a7(    .ovdd(NVCC_EMI2),

up_003_a4(    .ovdd(NVCC_EMI2),

up_004_a6(    .ovdd(NVCC_EMI2),

up_006_a5(    .ovdd(NVCC_EMI2),

up_007_a3(    .ovdd(NVCC_EMI2),

up_009_a0(    .ovdd(NVCC_EMI2),

up_010_a2(    .ovdd(NVCC_EMI2),

up_011_a1(    .ovdd(NVCC_EMI2),

up_013_ma10(    .ovdd(NVCC_EMI2),

up_014_cs3(    .ovdd(NVCC_EMI2),

up_015_cs2(    .ovdd(NVCC_EMI2),

up_017_cas(    .ovdd(NVCC_EMI2),

up_018_sdba1(    .ovdd(NVCC_EMI2),

up_019_sdba0(    .ovdd(NVCC_EMI2),

up_021_ras(    .ovdd(NVCC_EMI2),

up_022_sdwe(    .ovdd(NVCC_EMI2),

up_023_sdcke1(    .ovdd(NVCC_EMI2),

up_025_sdcke0(    .ovdd(NVCC_EMI2),

up_026_sdclk(    .ovdd(NVCC_EMI2),

up_028_sdqs0(    .ovdd(NVCC_EMI2),

up_029_sdqs1(    .ovdd(NVCC_EMI2),

[david_dicarlo]

I have submitted an internal ticket to our IC team to ask about the power supplies of pads A17-A25.

[fabio_estevam]

Hi Greg,

Let's check the IOMUX setup for the pins RDATA2 and RDATA3 in your case.

Please let us know which pads you use for RDATA2/3.

For example: if you use pad IOMUXC_SW_MUX_CTL_PAD_LD11 as RDATA2, then you need to set the MUX MODE as alt mode 5, according to the reference manual:

101: Select mux mode: ALT5 mux port: RDATA[2] of instance: fec.

One very important thing is that some mx25 pins require an additional setting of the select_input registers. In this example, we do need to configure it as the manual states:

NOTE: Pad LD11 is involved in Daisy Chain.

- Config Register IOMUXC_ESDHC2_IPP_DAT1_IN_SELECT_INPUT for mode ALT6.

- Config Register IOMUXC_FEC_FEC_RDATA_2_SELECT_INPUT for mode ALT5.

So you need to setup the IOMUXC_FEC_FEC_RDATA_2_SELECT_INPUT correctly.

This is a 2-bit register:

Selecting Pads Involved in Daisy Chain.

Instance: fec, In Pin: fec_rdata[2]

00: Selecting Pad: A20 for Mode: ALT7.

01: Selecting Pad: LD11 for Mode: ALT5.

10: Selecting Pad: SD1_CMD for Mode: ALT2.

as we want ALT5, then we need to write 01 to the register
IOMUXC_FEC_FEC_RDATA_2_SELECT_INPUT

Hope this example helps.

Regards,

Fabio Estevam

[gregungerer]

Hi Fabio,

[fabio_estevam]

Hi Greg,

Your last message does not appear in the forum.

Regards,

Fabio Estevam

[gregungerer]

Hi Fabian,

[fabio_estevam]

Hi Greg,

It seems that all of your replies are still missing.