iMX.8 Characteristics of CS polarity and CPHA=1 in SPI IF.

[YukioOyama]

Hello all,

I have now confirmed the use of i.MX8 Quad Max.

1,

In the datasheet, the LPSPI timing is illustrated with CS active high.

In the reference manual, the default value for CS polarity is active Low.

(CSPOL:00b)

Why is CS shown as active high in the data sheet?

I don't think it is common to use CS in Active High; does NXP's promotion of Active High convey any important message to me?

2,

Where can I get CPHA=1b timing chart?

I want to use it with CPHA=1b but I cannot find its timing chart in the datasheet. I want to check if the characteristics match with my slave device.
CPOL only reverses the polarity of CLK and does not change the timing, but CPHA shifts the phase and therefore changes the timing.

3,
And I cannot discover where to set CPOL and CPHA. At least it is not in the device tree.

Information on the material I am referring to is as follows;

<Datasheet>

i.MX 8QuadMax Industrial Applications Processors 

Data Sheet: Technical Data

Document Number: IMX8QMIEC
Rev. 1, 04/2022

<Reference Manual>

i.MX 8QuadMax Applications Processor Reference Manual

Document Number: IMX8QMRM
Rev. 0, 9/2021

Best Regards,

Yukio Oyama

[riteshmpatel]

Hi @YukioOyama ,

Hope you are doing well.

Please accept my apologies for delay in response.

Kindly see the answers to your questions as below: 

1. Can you please read the CSPOL value via devmem2 tool?

2. Timing parameters are valid for all modes using appropriate edge of the clock. Kindly refer Section 4.10.1.1 LPSPI Master mode of the i.MXQM datasheet.

3. You can add cpol and cpha in device tree, Please find the reference below:

spi-cpol;

spi-cpha;

Thanks & Regards,

Ritesh M Patel

[YukioOyama]

Hello Ritesh-san,

Thank you for remembering my case.

1,

Knowing the current value is not the intention of my question.

In 4.10.1.1, Despite the example of CPOL = 0b0, the CS in the timing chart is depicted as active high. Why are the assumptions and the diagram different?
Is NXP intentionally reversed in any way?

2,

Do you mean that the timing of 4.10.1.1 is promised any polarity?

3,

Thank you for telling me that I can indicate in the device tree.
Could you be more detail? For example, when mode=0 (CPOL=0, CPHA=0), how would you describe it?

Best Regards,

Yukio Oyama

[riteshmpatel]

Hi @YukioOyama,

Hope you are doing well.

Please see response to the queries below:

1. CPOL sets the polarity of Clock and CSPOL sets the polarity for CS. Kindly refer to the description of CPOL in Section 17.7.3.1.15.4 of Reference Manual.

2. As mentioned in the datasheet, Timing parameters will be valid for all four modes using appropriate edge of the clock. Kindly refer to the attached image for further clarification.

3. For device tree changes, By default CPOL and CPHA are disable, that means both will be 00.

If need to enable CPOL then add spi-cpol; in device tree. If need to enable CPHA then add spi-cpha; in device tree.

If need to enable both then add spi-cpol; and spi-cpha; in device tree.

Thanks & Regards,

Ritesh M Patel

[YukioOyama]

Hello Ritesh-san,

1,

I have changed the way I phrased my questions.

Do I need to worry about the chart not being drawn with the polarity of the register reset value?

2,

I understood that the same timings apply in all 4 modes, not just the polarity in the chart.

3,

I know what polarity each parameter changes.
I would like to know examples of how to describe them in the device tree.

Best Regards,

Yukio Oyama

[riteshmpatel · Accepted solution]

Hi @YukioOyama,

Hope you are doing well.

Please accept my apologies for the delay in response.

Please see below my response:

1. The timing diagram given in datasheet is an example of the specific configuration done through registers. This diagram does not resemble to the register reset values.

3. For CPOL = 1 and CPHA = 1
Add the below code in existing device tree node of SPI
spl-cpha;
spi-cpol;

For CPOL = 0 and CPHA = 1
Add the below code in existing device tree node of SPI
spl-cpha;

For CPOL = 1 and CPHA = 0
Add the below code in existing device tree node of SPI
spl-cpol;

For CPOL = 0 and CPHA = 0
No need to modify the device tree

Thanks & Regards,

Ritesh M Patel

[YukioOyama]

Hello Ritesh-san,

For 1,

I understood that the chart and the reset value were irrelevant. Thank you.

For3,

I finally understood that when I wrote each word, the value "1" was set.
I wondered why each word had no argument, but that was my misunderstanding. Thanks for explaining in detail.

I would close this case. Thank you for your explanation, it is very much appreciated.

Best Regards,

Yukio Oyama