iMX(6) SSI normal/network, I2S, 2-channels modes relations

[philippewicker]

Hello all,

I'm experimenting - in a bare-metal approach using the SDK 1.1 - with the SSI peripherals available in an iMX6Q SoC. My goal at the end is to use an SSI peripheral to output 24bits stereo audio, and possibly to input 24bits stereo audio using audio buffers as short as 32 frames. Currently I'm using an evaluation board which uses a TLV320AIC3007 codec (Texas Instrument). It is connected to AUDMUX5, so I can use SSI2 (which is connected by default to AUDMUX5 after a reset).

Now my problem is how I should configure  the SSI, specifically in order to be able to use the 2 sets of transmit (and receive) FIFOs (2-channels option).

I'm a bit puzzled by the settings in the SSIx_SCR register. Are these settings independent (I mean is any combination legal)? Do we need to activate the network mode in order to be able to use the 2-channels option?

If I have well understood, the I2S protocol implies a succession of left / right samples. In the case of the I2S "slave" mode, the RM (§61.8.1.4) says that the "normal/network" setting is overridden to "normal". In the case of the I2S "master" this "normal/network" mode setting is overridden to "network". In both cases (I2S slave or master) there's no mention of the 2-channels setting. Does that mean that when I2S is enabled the 2 FIFOs are always used whatever the 2-channels setting?

Sorry if my questions seems a bit unclear, but it just translate how I'm confused after the reading of the RM :smileyconfused:

Thanks,

Philippe

[宗標廖]

I am working on I2S slave mode and using L3.0.35_4.1.0 , by default SSI_SCR[3]=1 is set(Network mode is selected).

After the channel swap issue happened,I changed the BSP and set  SSI_SCR[3]=0, then the channel swap issue does not

happen any longer.

But in the IMX6SDLRM,there are descriptions as bellow:

--------------------------------------------------------------------

In I2S slave mode(SSI_SCR[6:5]=10), the following settings are internally overridden by

the hardware:

. Normal mode is selected (SSI_SCR[3]=0)

--------------------------------------------------------------------

My questions are:

Q1):

Is SSI_SCR[3] really overridden by internal hardware?

Q2):

Is there any relationship between channel swap and the setting of SSI_SCR[3] when work on I2S slave mode?

Best Regards,

ZongbiaoLiao

[justin_jiang]

My questions are:

Q1):

Is SSI_SCR[3] really overridden by internal hardware?

Yes.

Q2):

Is there any relationship between channel swap and the setting of SSI_SCR[3] when work on I2S slave mode?

No relationship. You can enable the dual-fifo mode which can avoid channel swap issue.

[saurabh206]

Hi karinavalencia​

Where can I find information about

"as i know, i2s master mode can't use i2s dual-fifo mode, only i2s slave mode(our default BSP) can use i2s dual-fifo mode."

[justin_jiang]

As I know, both master and slave mode can support dual-fifo mode.

[saurabh206]

Hi Qingrong

We are using SSI master mode, enable dual FIFO.

BSP is 3.10.17.

We are facing channel swap issue after reboot or power on/off.

Can you provide update on this?

Thanks

Saurabh

[justin_jiang]

In theory, the channel swap issue only happen when overrun/underrun occurs.

Is this issue only happen for dual FIFO mode or master mode?

[宗標廖]

Hello, Qingrong

Does the underrun only happen when SSI is working on Network mode?

(Could it happen on I2S slave mode?)

Best Regards,

ZongbiaoLiao

[justin_jiang]

On I2S slave mode, it also may happen.

[宗標廖]

Hi Qingrong

Could you help me?

Thank you!

[saurabh206]

Hi Qingrong

Yes, We are getting Underrun error at boot up time.

Dual FIFO mode is used and SSI master mode is setup.

Thanks

Saurabh

[justin_jiang]

Can you fix the underrun issue? Otherwise, when underrun occurs, you need reset SSI and start the DMA again.

This can avoid the channel swap issue.

[saurabh206]

Hi

Qingrong

I am not able to fixed the underrun issue.

We are seeing underrun after 30 to 40 reboot or power on issue.

Do you have any solution how to fix the underrun issue?

Thanks

Saurabh

[justin_jiang]

Hi Saurabh,

Since the underrun issue is related with your audio design.

You need review your hardware design and sw driver to fix it.

the workaroud for this issue is when the underrun happen, please reset SSI controller by re-configure all the registers.

[karina_valencia]

JiangJustin​ can you comment please?

[karina_valencia · Accepted solution]

Re: iMX(6) SSI normal/network, I2S, 2-channels modes relations

leige-b42127 Mar 12, 2014 7:30 PM (in response to jamesbone)

as i know, i2s master mode can't use i2s dual-fifo mode, only i2s slave mode(our default BSP) can use i2s dual-fifo mode.

[philippewicker]

Thanks for your answer,

I’ve been able to make it work with the following settings:

- SSI controller I2S master

- sample rate 44.1KHz

- word length 24 bits (real word length is 32 because of the I2S master setting)

- 2-channels mode, transmit FIFO 1 & 2 enabled (SCR.TCH_EN set to 1, SRCR.TFEN0 and TFEN1 set to 1)

I didn't try the SSI controller I2S slave mode.

Thanks

[shafi]

In my IMX6q Sabrelite board, i.MX6q SSI interface is Slave and my onboard codec SGTL5000 is master. In my BSP , file (sound/soc/imx/imx-ssi.c) I found that in the function " imx_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)" always the program controls goes to  "SND_SOC_DAIFMT_CBM_CFM" and it is setting the SSI interface as I2S slave. Can you please help me to configure IMX SSI interface as I2S master.

[ajithpv]

Hi shafi,

You can configure iMX SSI interface as I2S master by using "SND_SOC_DAIFMT_CBS_CFS" instead of "SND_SOC_DAIFMT_CBM_CFM"  :smileycheck:

Best regards,

Ajith P V

[shafi]

Hi Ajith,

Thank you somuch for your reply. I have given the "SND_SOC_DAIFMT_CBS_CFS" instead of "SND_SOC_DAIFMT_CBM_CFM" in the configuration file for SSI I2S master.  So, now I want to configure my audio codec sgtl5000 as I2S slave. What is the parameter I have to change it. As of now my sgtl5000 is I2S master. Then I can run my board as Master (IMX SSI as I2S Master) and SGTL5000 as I2S slave.

Thanks,

Shafi

[philippewicker]

Hi shafi k,

You should first carefully read the sgtl5000 data sheet you can find here:

http://cache.freescale.com/files/analog/doc/data_sheet/SGTL5000.pdf

There's also an AN giving programming tips about that chip:

http://cache.freescale.com/files/analog/doc/app_note/AN3663.pdf

I'm not familiar with this codec so I can't tell you exactly which register you have to program and how. After a short reading of the data sheet I'd say that the important registers are CHIP_CLK_CTRL and CHIP_I2S_CTRL. Not sure but it seems that the sgtl5000 needs a clock on the SYS_MCLK pin (some CODEC can derive their internal clock from the bit clock). This clock input is connected to the GPIO0_CLOCK0 signal. If you want to use the codec as a slave this clock must be a multiple of the sample rate. You cannot use the internal PLL to derive the sample rate clock because if you do so the codec must be set as the master. I'm not familiar with Linux for the iMX6, I don't know how this codec is programmed by Linux, and neither how the GPIO0_CLOCK0 is set by Linux. If you are lucky the GPIO0_CLOCK0 may already be set at a sample rate multiple. Another point which may be of importance is that when the SSI is I2S master, the real data bit number is 32, whatever the valid bit number. In my application, the word length is 24 but the actual length on the bus is 32. I've not seen any remarks on the data sheet about that.

HTH