i.mx91 uboot and linux soft Reset not working

[DavidFlir]

Problem - my software reset is not working.

When in uboot - typings `reset` stalls the system.

When in Linux - tpying `reboot` stalls the system.

I have wdog3 enabled in my device tree.,

&wdog3 {
	status = "okay";
};

Versioning: 

• Linux buildroot 6.12.20
• U-Boot 2025.04
• CPU: NXP i.MX91(31) Rev1.0 A55 at 1400 MHz   (<- Custom made board.)

Note:

for uboot I have the default `CONFIG_IMX_WATCHDOG=n`, because it doesn't seem supported.

All references referring to the watchdog are enabled, see below link.

Related topic here https://community.nxp.com/t5/i-MX-Processors/Watchdog-support-for-i-MX8QXP-MEK-under-U-Boot/td-p/124...

So my Linux config holds

For the Linux kernel there are SCU watchdog configuration options.

CONFIG_IMX2_WDT=y
CONFIG_IMX_SC_WDT=y
CONFIG_HAVE_ARM_SMCCC=y
CONFIG_IMX_SCU=y
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_CORE=y
CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y
CONFIG_WATCHDOG_OPEN_TIMEOUT=0

[DavidFlir · Accepted solution]

After digging in the i.MX 91 Applications Processor Reference Manual , I did not find a way to do a "warm reset" with the processor. I will close this issue, because we made a design fault by not connecting the WDOG_ANY pin which then could reset the processor via the POR_B-pin.

Conclusion:  Performing a software reset, requires the hardware lines to be in place.

Thanks to @Chavira for the quick reply and pointing out the missing link I was unaware of.

[DavidFlir]

Reading the often referenced Linux reference manual, I see:
The files I do not find are related to IMX8 Watchdog.
Also not here in the Sept 2025 release ->  https://github.com/nxp-imx/linux-imx/tree/lf-6.12.34-2.1.0/drivers/watchdog

So the documentation is outdated?

[Chavira]

Hi @DavidFlir,

Are you using an iMX8 or an iMX91?

In Table 25, you can see that we use the imx7ulp_wdt.c driver for iMX9 devices, which includes iMX91, iMX93, and iMX95.

For iMX8, we use the imx8_wdt.c driver, as its architecture is different from the iMX9 family.

[DavidFlir]

I am using the iMX91, so I don't need the non-existing imx8_wdt.c-driver.

[Chavira]

Hi @DavidFlir, 

Thank you for contacting NXP Support!

Are you currently using the PCA9451 PMIC?

Could you please confirm whether the power-up, power-down, and reset signals are behaving according to the specifications?

Regarding your software environment, please note that we do not provide official support for Buildroot. Our supported platform is the Yocto Project, which we recommend for development.
You can find all the relevant documentation here:

Embedded Linux for i.MX Applications Processors

To ensure compatibility and stability, we suggest porting our BSP to your custom hardware. This will help verify that the BSP functions correctly with your specific setup.

You might want to compare the device tree and kernel configuration of your setup with those of our EVK board. However, based on the symptoms, this could potentially be a hardware-related issue.

Would you be able to share your schematic? That would help us better understand the situation and provide more accurate guidance.

Best Regards,

Chavira

[DavidFlir]

@Chavira, thanks for reply.

I am not sure how this can be a hardware related error. The watchdog is purely software as far as I know. The procosser iMX91 detects a timeout and reboots itself. Where is the hardware link then?

We do not have a PCA9541 device.
The signals behave properly at boot-up since ... and I can already boot into Linux.

I have been comparing the device trees with the EVK examples but I did not find a difference so I come here for help.

a helpful link was this... https://community.nxp.com/t5/i-MX-Processors/i-MX93-Linux-reboot-not-working/m-p/2039359 , but my wdog3 is enabled and it still does not work.

There is also a wdog4 and wdog5, but enabling these prevents the board from booting.

wdog4: watchdog@424a0000 {
compatible = "fsl,imx93-wdt";
reg = <0x424a0000 0x10000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX91_CLK_WDOG4_GATE>;
timeout-sec = <40>;
status = "disabled";
};

wdog5: watchdog@424b0000 {
compatible = "fsl,imx93-wdt";
reg = <0x424b0000 0x10000>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX91_CLK_WDOG5_GATE>;
timeout-sec = <40>;
status = "disabled";
};


so thanks for tips... but it's not clear what the problem might be.

(Not posting schematics, since I don't think this is hardware related.)

[Chavira]

Hi @DavidFlir,

The reset mechanism in the iMX91 involves both software and hardware coordination. When a watchdog reset is triggered, the SoC asserts a low signal on the WDOG_B pin. This signal is routed to the PMIC, which then initiates a reset sequence across the power rails.

To ensure proper operation, your system's power-on, power-down, and reset sequences must comply with the specifications outlined in the iMX91 reference manuals.

Our PMICs are specifically designed for the iMX91 platform, so when configured correctly, you should not encounter issues related to reset behavior.

Best regards,
Chavira

[DavidFlir]

We do not have this WDOG_B pin (J18) connected, and we also do not use the PMIC.

We have another reset circuit based on a GPIO to reset USB,Ethernet,..

[Chavira]

Hi @DavidFlir,

That might be the issue. I understand you're not using a PMIC, but it's important to implement proper reset hardware to ensure all power sequences meet the specifications of the iMX91 chip.
If you have access to an iMX91-EVK or FRDM-iMX91 board, I recommend taking measurements of the power sequences. While these are documented in the reference manuals, comparing them with a working model can often help identify and resolve issues on a custom board.

Best regards,
Chavira

[DavidFlir]

@Chavira , I am looking to configure a pure SoftwareWatchdog that results in a processor reboot... Is there not a register I can set a '1` so the processor does a SW reboot?

I am looking at the "25.5.1 SRC GENERAL register descriptions" of the i.MX91 Applications Processor Reference...

[Chavira]

Hi @DavidFlir,

You can try using our Watchdog unit test to verify functionality.

If you're working with our BSP, the test should be located in the "Unit tests" folder at the root of the project directory.

Use case

./autorun-wdog.sh
or
./wdt_driver_test.out 1 2 0 &

The test is designed to trigger a system reset after approximately 3 seconds.
This is based on a 1-second timeout followed by a 2-second sleep

[DavidFlir]

I do not have my `WDOG_B`-pin connected on our design. So that will surely not work if it's based on the evk which does count on the hardware reset circuit with the PCA9451 PMIC...
(the code of wdt_driver_test is based on /dev/watchdog , which fails to work in my desig becnause of the above reason.)

So my idea is to rework this to a register write for the imx91 that would lead to a reset of the processor. But I do not know which register to write.

If such register does not exist, then I will have to make a hardware modification request..