[i.mx8mp] Unable to access multiple nand flash on u-boot

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[i.mx8mp] Unable to access multiple nand flash on u-boot

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junya
Contributor III

I have a custom board with a i.MX8MP and a KIOKXIA TH58NVG4S0HTAK0 which should be used as boot device.

Boot device : NAND FLASH 2GB (2 chip select, 1chip select is 1GB)

   (Image size to be written is 1.6 GB)

brunch:imx-linux-hardknott

manifesto:imx-5.10.35 2.0.0.xml

DISTRO:fsl-imx-wayland

MACHINE:mx8mpevk

 

Probably succeeded until u-boot was booted.

Reads and writes to NAND located in NAND_CE0 are successful.

However, CE1 fails...

The log of the success and failure is attached.

Am I doing something wrong with the confirmation?

 

Best regards.

  

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1 Solution
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junya
Contributor III

Hi, @Sanket_Parekh san.

Thank you very much!!

After applying the patch of u-boot you shared with me, this problem was resolved.

View solution in original post

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6 Replies
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junya
Contributor III

We found that there is a difference in AC characteristics when leading to CE0 and when leading to CE1.

(Image attached.)

CE1 is not working properly after sending the second cycle 30h of read operation.
Before the ready pin goes High, the CE1 pin goes Low and the read operation is started.
CE0 looks correct.

Therefore, I assume that the AC characteristic settings of CE0 and CE1 are different in the U-boot.

But I don't know how to fix it.

I need to know how to fix it.

 

Best regards.

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Sanket_Parekh
NXP TechSupport
NXP TechSupport
Hi @junya,
 
I hope you are doing well.
 
I have responded to your query in [i.mx8mp] Boot from nand flash.
 
Have you disabled internal pull-up in u-boot dts?
 
Please try in the kernel to see if CE1 works or not.
 
Thanks & Regards,
Sanket Parekh
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koichi_arima
Contributor I

Dear Sanket-san
This problem seems to be a problem with Uboot settings. Is it possible to share code, including settings such as defconfig of multiple NANDs verified by NXP, in order to speed up problem fix?

Thanks

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junya
Contributor III

Hi, @Sanket_Parekh .

Thank you for your help.

Have you disabled internal pull-up in u-boot dts?

Yes, i had already disabled internal pull. ( External pull-up are implemented.)

 

What do you think about the attached CE1 waveform?
Read accesses are initiated even though the memory is busy.

 

Best regards.

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Sanket_Parekh
NXP TechSupport
NXP TechSupport
Hi @junya,
 

I hope you are doing well.

It seems that Multiple chipselect or nand device support is not available in the nand driver in U-boot.

One needs to set DECOUPLE_CS  to decouple Chip Select from the DMA Channel. to enable multiple Chip Select.

It was fixed in the kernel with the below commit.
mtd: rawnand: gpmi: Fix the driver only sense CS0 R/B issue

One needs to make changes to u-boot for multiple CS. Please refer to the below patch.
 
I hope it helps!
 
Thanks & Regards,
Sanket Parekh
1,047 Views
junya
Contributor III

Hi, @Sanket_Parekh san.

Thank you very much!!

After applying the patch of u-boot you shared with me, this problem was resolved.

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