[i.mx8mp] Boot from nand flash

[junya]

I have a custom board with a i.MX8MP and a KIOKXIA TH58NVG4S0HTAK0 which should be used as boot device.

Boot device : NAND FLASH 2GB (2 chip select, 1chip select is 1GB)

　  (Image size to be written is 1.6 GB)

brunch：imx-linux-hardknott

manifesto：imx-5.10.35 2.0.0.xml

DISTRO：fsl-imx-wayland

MACHINE：mx8mpevk

We tried to download yocto image with uuu tool but only 1GB of nand flash was recognized.

   (Under these conditions, u-boot will boot up.)

This was due to the fact that CS1 was not multiplexed.

After modification, 2GB of nand flash is now recognized.

Next, we tried to boot, but it fails.
The following log was generated.

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

U-Boot SPL 2021.04-5.10.35-2.0.0+g3463140881 (Jun 08 2021 - 01:39:44 +0000)
DDRINFO: start DRAM init
DDRINFO: DRAM rate 3200MTS
DDRINFO:ddrphy calibration done
DDRINFO: ddrmix config done
SEC0: RNG instantiated
Normal Boot
WDT: Not found!
Trying to boot from BOOTROM
image offset 0x100000, pagesize 0x1000, ivt offset 0x0
ROMAPI: download failure offset 0x158000 size 0x1000
SPL: failed to boot from all boot devices
### ERROR ### Please RESET the board ###

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Is there anywhere else it should be fixed?

[Larisabrownb]

The Advanced Boot Options screen lets you start Windows in advanced troubleshooting modes. You can access the menu by turning on your computer and pressing the F8 key before Windows  love language test   starts. Some options, such as safe mode, start Windows in a limited state, where only the bare essentials are started.UEFI boot mode refers to the boot process used by UEFI firmware. UEFI stores all the information about initialization and startup in an . efi file that is saved on a special partition called EFI System Partition (ESP).

[Sanket_Parekh]

Hi @junya 

I hope you are doing well.

Please make sure that the board include<.h> configuration contains the below configuration in uboot.

(uboot-imx/include/configs/imx8mp_evk.h)

#define CONFIG_SYS_MAX_NAND_DEVICE     2

Please also share other changes and configurations made for 2 CS in NAND for further debugging.

Thanks & Regards,

Sanket Parekh

[junya]

Hi, @Sanket_Parekh 

Thank you for your reply.

＞#define CONFIG_SYS_MAX_NAND_DEVICE 2

Yes, this definition has been added.

No other modifications were made.

Perhaps NAND_CE1 is set to GPIO and is not functioning as chip enable.

Where do I change the pad setting?

[junya]

Hi, @Sanket_Parekh .

NAND_CE1 was set to chip enable.

After physically disconnecting the CS1 wire from the SoC to memory and booting up to U-Boot, I looked at the registers in the SoC and saw that the multiplexing was assigned to NAND_CE1.

But, NAND_CE1 has always been output low after power on.

Image attached.(D0:CE0 , D1:CE1, D2:RY/BY)

Therefore, I assume that CE0 and CE1 are active at the same time and cannot be boot.

Why NAND_CE1 output low?

[Sanket_Parekh]

Hi @junya 

I hope you are doing well.

Can you please clarify after which change, U-boot fails to boot?

One may also need to program nand fuse accordingly.

Please refer to 6.1.5.4.1 NAND eFUSE configuration in i.MX 8M Plus Applications Processor Reference Manual.

Also refer to NAND_CS_NUM [0x4B0] fuse in Table 6-33. Boot Fusemap in i.MX 8M Plus Applications Processor Reference Manual.

Thanks & Regards,

Sanket Parekh

[junya]

Hi, @Sanket_Parekh .

Thank you for your helping.

It's not going well.

Can you please clarify after which change, U-boot fails to boot?

The following is modified to nand boot.

  - imx8mp-evk.dts

          Add line 282, 343

  - imx8mp_evk.h

          Modify line 242, 

                #define CONFIG_SYS_MAX_NAND_DEVICE 2

  - nand_ids.c

          Add line 57 ~59

I am not sure why fuse boot is relevant.
Are you saying that internal boot does not support multiple nand devices?

When the boot mode is set to NAND boot and power is turned on, does the NAND_CE1 pad function as a GPIO? (output? input?)
Or does it function as NAND_CE1?

Best regards.

[junya]

Hi, @Sanket_Parekh .

In the nand boot, until the u-boot setting is reflected, NAND_CE1 seems to be a gpio setting. (input pin pull-down).
So by pulling up NAND_CE1 externally, I was able to successfully boot u-boot.
However, there is the next issue after that.

[i.mx8mp] Unable to access multiple nand flash on ... - NXP Community

[Sanket_Parekh]

Hi @junya,

I hope you are doing well.

It is required to pull up NAND_CE externally.

From the dts, It seems that you have also enabled internal pull-up.

MX8MP_IOMUXC_NAND_CE0_B__NAND_CE0_B 0x000001d6
MX8MP_IOMUXC_NAND_CE1_B__NAND_CE1_B 0x000001d6

Please refer to pinctrl_gpmi_nand node in imx8mp-ddr4-evk.dts for pad settings.

Please close this case.

We will discuss this issue further on [i.mx8mp] Unable to access multiple nand flash on ... - NXP Community

Thanks & Regards,

Sanket Parekh

[junya]

Hi, @Sanket_Parekh .

Thank you for your support.

It is required to pull up NAND_CE externally.

Yes, Until the port setting is reflected in u-boot, it is a GPIO input setting, so an external pull-up is necessary.

Please close this case.

Please tell me one last thing.
Is it my understanding that I don't need to set up fuse. Is that correct?

[Sanket_Parekh]

Hi @junya,

I hope you are doing well.

Is it my understanding that I don't need to set up a fuse? Is that correct?
[Ans]: One needs to set up fuses, As it is the only way for ROM code to know about custom NAND flash.
           One needs to configure various parameters for custom NAND such as NAND_CS_NUM, NAND_GPMI_DDR_DLL_VAL , NAND_RST_TIME  NAND_READ_RETRY_SEQ_ID, NAND_ROW_ADDR_BYTES, etc...

Please refer to 6.1.5.4.1 NAND eFUSE configuration and Table 6-33. Boot Fusemap in i.MX 8M Plus Applications Processor Reference Manual.

One can also see Boot Mode and CFG Switch sheet [page 21] in i.MX 8M Plus EVK Base Board Design Files

Yes, Until the port setting is reflected in u-boot, it is a GPIO input setting, so an external pull-up is necessary.
=> NAND PAD will act as NAND functional pins and not as normal GPIO during ROM boot.

Please make a note that at boot time only CS0 is supported.

Please refer to 4.2 Boot device interface allocation in i.MX 8M Plus Applications Processor Datasheet.

Have you tried removing the internal pull-up from the pinctrl_gpmi_nand node in u-boot the device tree?

Thanks & Regards,
Sanket Parekh

[junya]

[Ans]: One needs to set up fuses, As it is the only way for ROM code to know about custom NAND flash.

What is the custom NAND flash ?

Do you mean multiple memory?

Is fuse setting always required for multiple memory?

(Sorry for all the questions.)

Please make a note that at boot time only CS0 is supported.

Yes, so CS1 is not supported at boot time, I think it is a GPIO configuration.

[junya]

Hi, @Sanket_Parekh  san.

I have tried fuse-boot.

However, the phenomenon remained the same and the timing of access to CE1 was not correct.

I show fuse parameters under the below.

470h -> 10004140h

4A0h -> 00001E00h

4B0h -> 00000C79h

Other parameters remain at reset values.

Best regards.

[Sanket_Parekh · Accepted solution]

Hi @junya,

I hope you are doing well.

Fuse settings seem correct, As the board boots properly till U-boot, This issue could not be due to the fuse,

It could be due to a configuration issue in u-boot.

We will discuss this query further in the below post.

https://community.nxp.com/t5/i-MX-Processors/i-mx8mp-Unable-to-access-multiple-nand-flash-on-u-boot/...

Hence, Please close this case to avoid duplicate replies.

Thanks & Regards,

Sanket Parekh