i.mx6ull evk dram data 7 and data 2 swapped

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i.mx6ull evk dram data 7 and data 2 swapped

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Contributor V

I'm really confused about a discrepancy I'm seeing between the eval board schematic and layout.  Per the DDR3L datasheet and the i.mx6ULL datasheet, the DDR Data07 should connect from pad U4 on the i.mx6ull to pad H7 on the 96-pin memory (which seems to be a standard DDR pinout).  Likewise, DDR Data02 should connect frmo pad T6 on the i.mx6ull to pad F2 on the DDR3L IC.

Here's what's strange.  The datasheets agree with that, the EVK schematic agrees with that BUT the actual layout of the EVK CM module (i.e. the module that has the processor and DRAM) has them swapped, and when I inspect the physical board, what is manufactured follows the layout, and yet everything works.  how can this be??

I'm in the middle of laying out my own board, and this discrepancy has me really confused and it's holding things up.  Can someone clarify why and how this works?  The i.mx6ull datasheet clearly shows that the DRAM pads are no-mux. Since the actual eval board works that tells me that not does the datasheet have to be wrong, the schematic has to be wrong too and somehow the designer(s) deviated from the schematic.

I'm in a really pinch here. Someone please help!!

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NXP TechSupport
NXP TechSupport

Hello David Luberger,

If I understood your question correctly, I think the answer may be found on the i.MX6ULL Hardware Development Guide (link below). Specifically, section 3.5.1.

https://www.nxp.com/docs/en/user-guide/IMX6ULLHDG.pdf

The nature of DDR3 memories allow for swapping the data bus lines within bytes to make routing easier. Just keep in mind that the lowest bit of each byte must be aligned between the i.MX 6ULL and DDR chips. For example, D0 of i.MX 6ULL to D0 of DDR chip, D8 of i.MX 6ULL to D8 of DDR chip. This to allow hardware write leveling, which is performed in the lowest order bit of each byte.

The swapping should be listed on the schematic, but perhaps this change on the layout was overlook. It is common for the swapping to be determined only after the layout has been started and then the actual swap is listed on the schematic.

I hope this helps!

Regards,

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Contributor V

Ok thanks. That's very obscure. I've read the hardware development guide before and I guess that part didn't sink in. I'm not sure I understand what, if anything, must be done in software to accomodate this change. Do I have to change something in the kernel device tree as I have to do with iomux and other pin configurations? If I leave the pins swapped as they are how do I modify a "clean" device tree? If I put them back to match the original schematic, how do I modify the EVK device tree to adapt it to my board? The HDG just says that a register has to be changed, but I haven't messed with registers at all, and have been updating my board changes in the device tree and nowhere else prior to compiling the kernel.

David Luberger | Senior Electrical Engineer

Meriam Process Technologies, a Scott Fetzer company

Main Line: 216.281.1100

Direct Line: 216.928.2237

Fax 216.281.0228

Email: DLuberger@meriam.com<mailto:DLuberger@meriam.com>

Product info available | www.meriam.com<http://www.meriam.com/>;

Providing Innovative, Reliable, Cost Effective Measurement & Calibration Solutions Since 1911

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NXP TechSupport
NXP TechSupport

Hello David Luberger,

I understand how this sounds a bit obscure. Swapping signals is a serious matter in general, the difference with signals within a same byte of the DDR3 is that due to the nature of memories swapping the data lines would just route to a different physical memory location and all memory locations within the same byte group are identical (you wouldn’t need to make changes to the pinmux configuration or to the device tree). PCB designers take advantage of this as DDR signals are some of the toughest to route as these are high speed signals which have several constraints to be considered.

I hope this information helps!

Regards,

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Contributor V

Ok just to be clear, as this seems to be what I'm finding elsewhere: swapping bits within either the upper or lower data byte (within the byte, but not to another byte) requires no software changes right? The CPU will be completely agnostic of this change, correct? So I can swap individual bits (except 0, 7, 8, and 16) within a byte and this would be completely transparent to the DDR controller, the linux kernel, etc? I just want to make sure that I don't have to tell any software person that I did this.

David Luberger | Senior Electrical Engineer

Meriam Process Technologies, a Scott Fetzer company

Main Line: 216.281.1100

Direct Line: 216.928.2237

Fax 216.281.0228

Email: DLuberger@meriam.com<mailto:DLuberger@meriam.com>

Product info available | www.meriam.com<http://www.meriam.com/>;

Providing Innovative, Reliable, Cost Effective Measurement & Calibration Solutions Since 1911

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NXP TechSupport
NXP TechSupport

Hello David Luberger,

Correct, you can swap individual bits within a byte (except for the lowest bit of each byte) without any software changes.

(Just as a note, it is a good practice to update the schematic as to reflect the actual routing so it can be an accurate depiction of what is implemented on the board)

Regards,

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