i.mx6s DQS gating calibration ERROR FOUND

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i.mx6s DQS gating calibration ERROR FOUND

1,892 Views
raodejian
Contributor I

Hi,

My i.mx6 core board has DDR issue when running stress tester, it’s similar with other people’s who discussed in old thread. The difference is Quad and Dual can working with 1.2GHz processor and DDR stress test up to 628MHz, when I replace the processor by Solo or DualLite on same core board then the DQS gating calibration issue occurred.


I am confused does there any hardware issue made this strange issue? My test conditions as below,

  1. DDR Stress Tester: V2.0-RC1 and v1.0.3
  2. Core board configuration:

     * CPU: MCIMX6S5EVM10AB/AC silicon version v1.2

     * DDR RAM: MT41K256M16HA-125:E 2pcs

     * DDR RAM: MT41K128M16JT-125 IT:K 2pcs

     *i-NAND: SDIN7DU2

     *PMU: MMPF0100-F0EP

3. The core board follow Freescale SDP reference design

4. i.MX6DQSDL DDR3 Script Aid V0.10

5. DDR Stress Tester log

222.jpg

============================================
        DDR Stress Test (2.0.0)
        Build: Jun 11 2015, 23:33:58
        Freescale Semiconductor, Inc.
============================================

============================================
        Chip ID
DIGPROG(0x020c8260) = 0x00610002
CHIP ID = i.MX6 Solo/DualLite (0x61)
Internal Revision = TO1.2
============================================

============================================
        Boot Configuration
SRC_SBMR1(0x020d8004) = 0x020078f0
SRC_SBMR2(0x020d801c) = 0x22000001
============================================

ARM Clock set to 1GHz

============================================
        DDR configuration
BOOT_CFG3[5-4]: 0x00, Single DDR channel.
DDR type is DDR3
Data width: 32, bank num: 8
Row size: 14, col size: 10
Chip select CSD0 is used
Density per chip select: 512MB
============================================

Current Tempareture: 43
============================================

DDR Freq: 396 MHz

ddr_mr1=0x00000000
Start write leveling calibration...
running Write level HW calibration
Write leveling calibration completed
    MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x00440049
    MMDC_MPWLDECTRL1 ch0 (0x021b0810) = 0x003A003F
Write DQS delay reult:
   Write DQS0 delay: 73/256 CK
   Write DQS1 delay: 68/256 CK
   Write DQS2 delay: 63/256 CK
   Write DQS3 delay: 58/256 CK

Starting DQS gating calibration
. . . . . . . . . . . . . . ERROR FOUND, we can't get suitable value !!!!
dram test fails for all values.

Error: failed during ddr calibration

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2 Replies

878 Views
igorpadykov
NXP Employee
NXP Employee

HI rao

in general such error may be caused by noise and one can ignore it

if other tests passed. In particular sect.5.1.1 AN4397

Common Hardware Design for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite

states:

"when migrating the i.MX 6Dual/6Quad hardware design to the i.MX 6Solo, the four DDR3 devices

in the upper 32 bits may not be populated (DNP), but this will leave layout stubs that may affect DDR3

performance. Ideally, the layout should be modified to remove these stubs."

Additionally one can  :

- verify the PCB design using "MX6 DRAM Bus Length Check" sheet in

"HW Design Checking List for i.Mx6DQSDL Rev2.7.xlsx"

  https://community.freescale.com/docs/DOC-93819

   https://community.freescale.com/servlet/JiveServlet/downloadBody/93819-102-13-18441/HW%20Design%20Ch...

- try using different drive strength for DRAM signals for both  i.MX6 and DRAM part.

- try different DDR_SEL options  (11 or 10).

Best regards

igor

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877 Views
raodejian
Contributor I

Hi igor,

Thanks for your analysis and suggestions.


Also we found the reminder of noise which issue by upper 32 bits stubs in common hardware design guide, we plan to fix this issue by new independent
32bit PCB layout. I will update the result later. Thanks for your kindly support.

Best Regards,

Dejian

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