i.mx6q/i.mx6d

[flash_rah]

Could you tell - is each CPU core has it's own MMU or all cores has common MMU?

Is it possible to setup MMU table next way:

- CPU0 has full access memory region and read only memory region,

- CPU1 has full access memory region and write only memory region.

Read only [CPU0]/write only[CPU1] are intersected in memory map to implement inter-core communication.

Do you have code example to setup MMU on CPU1-3 (if is it possible) and sets different permissions to DDR3 memory access?

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Alex Buraga

[AnsonHuang]

Each core has its own MMU, and I think it is possible to do what you want, but it is complicated and I did not have example code, can I know what is the detail requirement of your use case? On Linux, there is per CPU data region what has private data for each CPU, does that meet your requirement?

[MikeJones]

It would be very helpful to have an app note on using L1/L2/MMU in multicore applications. It should cover page tables and how to handle that if there is MMU per core. Do you share the table, duplicate the table, etc. Also, the big issue, one I am having, is order of cleaning, invalidating, and enabling things. It is very hard to debug a failure due to improper setup.

An alternative would be to make the SDK primes example work with L1/L2/MMU so we have an example of the proper order of setup. Include the L2 code posted in this forum. Put notes in the code why things are in a certain order. For example, do you invalidate the dcache before or after enable? Put a note explaining the order for each line in the code so we understand what is happening.

The SDK is very helpful, it just needs more multicore examples. After all, these are multicore devices :-)

I don't want to reverse engineer Linux to learn how to set this up for a bare iron application.

[AnsonHuang]

Hi, Mike

     I think you can look into our linux BSP code of how to enable multi cores, take v3.0.35 release for example, you can refer to file: arch/arm/mach-mx6/headsmp.S and arch/arm/mach-mx6/platsmp.c, then entry is boot_secondary routine. Yes, we need to invalidate dcache before enabling it, as when power up, dcache is not in a clean state. For app note of using L1/L2/MMU in multicore, I think there are many DOC about SMP system in the internet, it is hard to describe it to a very detail level via this discussion. You can also look into uboot code or linux kernel boot up process to see how these cache/mmu should be enabled.

[flash_rah]

Mr. Huang, I want to implement Multi-OS software so I looking a best way for inter-processor communication.

I.e., i want to use 2 of 4 cores in SMP mode to run Linux & Qt based applications, and another 2 cores for hard realtime data filtering (FreeRTOS or baremetal applications).

I think MMU is comfort instrument to avoid "kernel panic" and another memory problems.

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As first step I want create baremetal program which allows every core to use several buffers to exchange data in Core-to-Core format in concurrent way.

Now I study MMU, SNOOP and Softwate Interrupt documentation.