i.mx6Solo VDD_PU_CAP cycling on / off

[ThomasG1z]

Hi,

on a custom board I see that VDD_PU cap is cycling on and off and wonder if that behavior is expected?

Running Linux 4.9.11.ga.

It cycles in periods of 1 to 1.5s when running a QT app with eglfs. When not running the app it stays off (~0.20V)

Looking at the PMU_REG_CORE with devregs the VDD_PU bit-field (REG1_TARG) toggles as well, between 00 and 26 (1175mV), e.g.

0x020c8140     =0x004c0012

0x020c8140     =0x004c2612

Using internal LDOs, no PMIC. SOC_IN supplied by 1.38V fixed regulator.

Is this behavior expected, and is it managed like this?

[igorpadykov]

Hi ThomasG1z

yes this is correct behavior, as nxp linux turns off VDD_PU_CAP

when vpu/gpu modules are not used, one can look on Figure 51-1. Power system

overview i.MX6SDL Reference Manual

http://www.nxp.com/assets/documents/data/en/reference-manuals/IMX6SDLRM.pdf

Best regards
igor
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------