i.mx6Q PCIe clock

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i.mx6Q PCIe clock

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DavorBogavac
NXP Employee
NXP Employee

Got following questions from customr Dyson. Can you please help me to answer them?

With regard to PCIe….

  • The CLK1_P/N and CLK2_P/N input and output electrical specifications appear to be missing from the EC spec, could you please supply?
  • The evaluation boards use CLK1_P/N output for PCI-e clock generation. But the HDG and eval schematics indicate that this clock is not PCIe compliant. In what way is this clock not PCIe compliant, e.g. voltage levels, jitter etc.? How can we determine whether this clock would be good enough to drive our particular device?
  • Is there any guidance on termination schemes when using this clock as an input or as an output, for example:
    • If the clock source driving the iMX6 input is LVDS, HCSL or HSTL
    • If the clock receiver being driven by the iMX6 output is LVDS, HCSL etc
Best Regards
Davor
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2 Replies

796 Views
Yuri
NXP TechSupport
NXP TechSupport

Hello,

1.

  According to Hardware Development Guide for i.MX6 in Table 2-7 (Oscillator and clock recommendations:

"CLK1_P/CLK1_N and CLK2_P/CLK2_N are LVDS input/output differential pairs compatible with
TIA/EIA-644 standard. The frequency range is 0 to 600 MHz.
Alternatively, a single-ended signal can be used to drive a CLKx_P input. In this case, the corresponding
CLKx_N input should be tied to a constant voltage level equal to 50% of VDD_HIGH_CAP. Termination
should be provided with high-frequency signals. See the LVDS pad electrical specification in the data
sheet for further details."


http://cache.nxp.com/assets/documents/data/en/user-guides/IMX6DQ6SDLHDG.pdf

2.

  HW_Design_Checking_List_for_i.MX6DQP6DQ6SDL Rev 3.1 contains useful recommendations about
using (external) PCIe clock :
 "Due to CLKx_P/N is LVDS port and don't match with PCIe reference clock specification. For PCIe Gen1
application, following low cost solution can be used(DC bias and AC impedance should be considered).  
Please refer to "HW_Design_Checking_List_for_i.MX6DQP6DQ6SDL Rev3.1.xlsx", sheet "Schematic",
Ref12 for more info."
   "PCIe reference clock solution which provided by CLKx_N/P of i.MX6 chip can't pass PCIe Gen2
compliance test.  Recommend using external PCIe 2.0/3.0 clock generator with 2 HCSL outputs solution.
One clock channel connect to i.MX6 as a reference input, please click Ref14
("HW_Design_Checking_List_for_i.MX6DQP6DQ6SDL Rev3.1.xlsx") for reference circuit.
Another clock channel should connect to PCIe connector, please contact generator vendor for detailed
design guide."


 https://community.nxp.com/docs/DOC-93819 

3.

How to interface HCSL to LVDS for IDT timing devices | IDT 


Have a great day,
Yuri

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796 Views
DavorBogavac
NXP Employee
NXP Employee

Thank you. It's evident that you are much better than I am at researching existing content.  

Best Regards
Davor