i.mx6 : RED/BLUE/GREEN bit positions in parallel display output

[kyu-myounglee]

Hi,

I want to connect triple 8bit Video DAC to i.mx6 for VGA output.

For schematic drawing, I have to know which portion of 24bit parallel display data pin(DISP0_DAT[23:0]) is corresponding to each color component(RED/GREEN/BLUE).

I couldn't find the information in the i.mx6 reference manual.

After searching this community, I found the following information.

Table 2 in Different Display Configurations on i.MX35 Linux PDK(AN3974, http://cache.freescale.com/files/dsp/doc/app_note/AN3974.pdf )

I can guess the following pin map in i.mx6 based on the table.

DISP0_DAT[23:16] => RED[7:0]

DISP0_DAT[15:8] => GREEN[7:0]

DISP0_DAT[7:0] => BLUE[7:0]

But because the table describes only i.mx35(not i.mx6), I'm not sure that my guess is correct in i.mx6.

So I want someone with authority to convince me that I can draw schematic of the i.mx6 board based on the information above.

[Yuri · Accepted solution]

Display (color bit mapping is software configurable. When configuring display output pins,

the following should be taken into account.

1.

General scheme is shown on Figure 37-32 (Mapping scheme) of the i.MX6DQRM.

2.

From Table 37-25 (DC template's fields description) :

«The MAPPING field holds a pointer to a register holding 3 fields: MAPPING_PNTR_BYTE0_X,

MAPPING_PNTR_BYTE1_X, MAPPING_PNTR_BYTE2_X. This pointers point to sets of OFFSET and

MASK parameters that define the mapping scheme. MAPPING =0 means that mapping is disabled.»

3.

Section 37.4.7.5.1 (Bus Mapping Unit) describes the mapping feature in more details.

On the Figure 37-32 (Mapping scheme), microcode field MAPPING = 2.

That is, register IPUx_DC_MAP_CONF_1 should be used for configuring; please refer to section 37.5.336

[DC Mapping Configuration Register 1 (IPUx_DC_MAP_CONF_1)] of the Reference Manual.

As an example let we set :

MAPPING_PNTR_BYTE2_2 = 2

MAPPING_PNTR_BYTE1_2 = 1

MAPPING_PNTR_BYTE0_2 = 0

then

IPUx_DC_MAP_CONF_15 register should be set as following :

(section 37.5.350 DC Mapping Configuration Register 15 (IPUx_DC_MAP_CONF_15))

MD_OFFSET_1 = 0x0D ; MD_MASK_1 = 0xFC

MD_OFFSET_0 = 0x05 ; MD_MASK_0 = 0xFC

IPUx_DC_MAP_CONF_16 :

MD_OFFSET_2 = 0x16 ; MD_MASK_2 = 0xFC

4.

Please refer to  Chapter 18 (Configuring the IPU Driver) of "iMX6_Firmware_Guide.pdf" in the Platform SDK.

https://www.freescale.com/webapp/Download?colCode=i.MX6_PLATFORM_SDK&location=null

http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=i.MX6Q&fpsp=1&tab=Design_Tools_Tab

5.

  Please use i.MX6 Datasheet(s) to define typical IPU display output formats.

For example please take a look at section 4.11.10.4 (IPU Display Interface

Signal Mapping) of IMX6SDLCEC (Rev. 2.1, 05/2013).

[kyu-myounglee]

Thank you for great answer.