i.mx6 LCD support

[MaxChou]

Hi  All

I try to use DISP0 interface to turn on a 1920x1080,

I can't get the correct display,

so I measure the pixel clock,

it is 148.5MHz,

but it seems unstable,

when I set it to 1280x720(74MHz),and 1360x768(85MHz)

the clock looks good,

I could get the correct display,

so I have the below question,

what is the max pixel clock out of DISP_CLK ??

Could I use it to support a 1920x1080 panel ?

Sincerely,Max Chou

[lily_zhang]

Do you have your 1080p display spec?

[MaxChou]

Hi  Sirs

We test several display modes(1024x768,1280x720,1360x768,1280x1024,1920x1600,1920x1080) and measure DISP_CLK,

We could get correct display on 1024x768,1280x720,1360x768,

But If we set clock rate over 100MHz(1280x1024,1920x1600,1920x1080),

We can see the jitter like above waveform,

But the clock rate is correct,

It seems i.mx6 PLL has some problem.

It is unstable

Could you tell me where could I modify ?

All display timing is followed “VESA and Industry Standards and Guidelines for Computer Display Monitor Timing (DMT)”.

/////////////////1080P timing (refer ldb.c)////////////////////////////////////

{

        "LCD-1080P60", 60, 1920, 1080, 7692,

        100, 40,

        30, 3,

        10, 2,

        0,

        FB_VMODE_NONINTERLACED,

        FB_MODE_IS_DETAILED,},

//////////////////////////////////////////////////////////////////////////

Best Regards,

Max Chou

[lily_zhang]

Hello, Max:

What’s your pixel clock tree (from PLL to pixel clock)?

If you are using Android, you can try to use “powerdebug –d -c” to read clock information.

For example,

    `-- pll2_528_bus_main_clk (flags:0x0, usecount:3, rate: 528.000000 MHZ)

        |-- pll2_pfd_352M (flags:0x0, usecount:1, rate: 452.571411 MHZ)

        |  |-- ldb_di0_clk (flags:0x24, usecount:0, rate: 64.653061 MHZ)

        |    `-- ldb_di1_clk (flags:0x24, usecount:2, rate: 64.653061 MHZ)

        |        `-- ipu1_di_clk_1 (flags:0x24, usecount:1, rate: 64.653061 MHZ)

Best Regards

Lily Zhang

[MaxChou]

Hi  Sirs,

Please help check it, thank you!!

Clock Tree :

**********

/

|-- ckih_clk (flags:0x0, usecount:0, rate: 0.000000 HZ)

|-- ckih2_clk (flags:0x0, usecount:0, rate: 0.000000 HZ)

|-- ckil_clk (flags:0x0, usecount:0, rate: 32.768002 KHZ)

|-- caam_mem_clk (flags:0x0, usecount:0, rate: 0.000000 HZ)

|-- mlb150_clk (flags:0x0, usecount:0, rate: 0.000000 HZ)

|-- anaclk_1 (flags:0x0, usecount:0, rate: 0.000000 HZ)

|-- anaclk_2 (flags:0x0, usecount:0, rate: 0.000000 HZ)

`-- osc_clk (flags:0x0, usecount:7, rate: 24.000000 MHZ)

    |-- pll6_mlb150_main_clk (flags:0x0, usecount:0, rate: 24.000000 MHZ)

    |-- pll7_usb_host_main_clk (flags:0x0, usecount:0, rate: 480.000000 MHZ)

    |-- pll1_sys_main_clk (flags:0x0, usecount:1, rate: 792.000000 MHZ)

   |    `-- pll1_sw_clk (flags:0x0, usecount:1, rate: 792.000000 MHZ)

    |        `-- cpu_clk (flags:0x0, usecount:1, rate: 792.000000 MHZ)

    |            `-- twd_clk (flags:0x0, usecount:0, rate: 396.000000 MHZ)

    |-- pll4_audio_main_clk (flags:0x0, usecount:0, rate: 176.000000 MHZ)

    |    `-- asrc_clk (flags:0x0, usecount:0, rate: 176.000000 MHZ)

    |-- gpt_clk (flags:0x0, usecount:1, rate: 3.000000 MHZ)

    |-- pll8_enet_main_clk (flags:0x0, usecount:1, rate: 24.000000 MHZ)

    |   |-- enet_clk (flags:0x24, usecount:1, rate: 50.000000 MHZ)

    |    `-- sata_clk (flags:0x24, usecount:0, rate: 24.000000 MHZ)

    |-- pll3_usb_otg_main_clk (flags:0x0, usecount:4, rate: 480.000000 MHZ)

    |   |-- pll3_pfd_720M (flags:0x0, usecount:0, rate: 720.000000 MHZ)

    |   |-- pll3_pfd_508M (flags:0x0, usecount:0, rate: 508.235291 MHZ)

    |   |   |-- ssi1_clk (flags:0x72, usecount:0, rate: 63.529411 MHZ)

    |   |   |-- ssi2_clk (flags:0x72, usecount:0, rate: 63.529411 MHZ)

    |   |    `-- ssi3_clk (flags:0x72, usecount:0, rate: 63.529411 MHZ)

    |   |-- pll3_pfd_454M (flags:0x0, usecount:0, rate: 454.736847 MHZ)

    |   |    `-- spdif0_clk_0 (flags:0x24, usecount:0, rate: 28.421053 MHZ)

    |   |-- pll3_sw_clk (flags:0x0, usecount:1, rate: 480.000000 MHZ)

    |   |   |-- pll3_120M (flags:0x0, usecount:0, rate: 120.000000 MHZ)

    |   |   |-- esai_clk (flags:0x0, usecount:0, rate: 30.000000 MHZ)

    |   |   |-- pll3_60M (flags:0x0, usecount:0, rate: 60.000000 MHZ)

    |   |   |   |-- can_clk_root (flags:0x0, usecount:0, rate: 30.000000 MHZ)

    |   |   |   |   |-- can1_module_clk (flags:0x24, usecount:0, rate: 30.000000 MHZ)

    |   |   |   |    `-- can2_module_clk (flags:0x24, usecount:0, rate: 30.000000 MHZ)

    |   |   |   |-- ecspi0_clk (flags:0x0, usecount:0, rate: 60.000000 MHZ)

    |   |   |   |-- ecspi1_clk (flags:0x0, usecount:0, rate: 60.000000 MHZ)

    |   |   |   |-- ecspi2_clk (flags:0x0, usecount:0, rate: 60.000000 MHZ)

    |   |   |   |-- ecspi3_clk (flags:0x0, usecount:0, rate: 60.000000 MHZ)

    |   |   |    `-- ecspi4_clk (flags:0x0, usecount:0, rate: 60.000000 MHZ)

    |   |   |-- pll3_80M (flags:0x0, usecount:1, rate: 80.000000 MHZ)

    |   |   |    `-- uart_clk (flags:0x0, usecount:2, rate: 80.000000 MHZ)

   |   |    `-- asrc_serial_clk (flags:0x0, usecount:0, rate: 7.500000 MHZ)

    |   |-- gpu2d_core_clk (flags:0x24, usecount:0, rate: 480.000000 MHZ)

    |   |-- usb_phy1_clk (flags:0x0, usecount:1, rate: 1.010065 GHZ)

    |   |-- usb_phy3_clk (flags:0x0, usecount:0, rate: 1.010065 GHZ)

    |   |-- usb_phy4_clk (flags:0x0, usecount:0, rate: 1.010065 GHZ)

    |    `-- pll3_pfd_540M (flags:0x0, usecount:1, rate: 540.000000 MHZ)

    |       |-- hdmi_isfr_clk (flags:0x0, usecount:0, rate: 540.000000 MHZ)

    |        `-- mipi_pllref_clk (flags:0x0, usecount:1, rate: 540.000000 MHZ)

    |-- clko2_clk (flags:0x0, usecount:1, rate: 24.000000 MHZ)

    |    `-- clko_clk (flags:0x0, usecount:0, rate: 24.000000 MHZ)

    |-- pll5_video_main_clk (flags:0x0, usecount:1, rate: 297.000000 MHZ)

    |   |-- ipu1_di_clk_1 (flags:0x24, usecount:0, rate: 99.000000 MHZ)

    |   |-- ipu2_di_clk_0 (flags:0x24, usecount:0, rate: 99.000000 MHZ)

    |   |-- ipu2_di_clk_1 (flags:0x24, usecount:0, rate: 99.000000 MHZ)

    |    `-- ipu1_di_clk_0 (flags:0x24, usecount:1, rate: 148.500000 MHZ)

    |        `-- ipu1_pixel_clk_0 (flags:0x0, usecount:1, rate: 148.500000 MHZ)

     `-- pll2_528_bus_main_clk (flags:0x0, usecount:2, rate: 528.000000 MHZ)

        |-- pll2_pfd_352M (flags:0x0, usecount:0, rate: 452.571411 MHZ)

        |   |-- ldb_di0_clk (flags:0x24, usecount:0, rate: 64.653061 MHZ)

        |    `-- ldb_di1_clk (flags:0x24, usecount:0, rate: 64.653061 MHZ)

        |-- pll2_pfd_594M (flags:0x0, usecount:0, rate: 594.000000 MHZ)

        |    `-- gpu3d_shader_clk (flags:0x24, usecount:0, rate: 594.000000 MHZ)

        |-- pll2_pfd_400M (flags:0x0, usecount:1, rate: 396.000000 MHZ)

        |   |-- pll2_200M (flags:0x0, usecount:0, rate: 198.000000 MHZ)

        |   |-- mmdc_ch1_axi_clk (flags:0x0, usecount:0, rate: 396.000000 MHZ)

        |   |-- usdhc1_clk (flags:0x0, usecount:0, rate: 198.000000 MHZ)

        |   |-- usdhc2_clk (flags:0x0, usecount:0, rate: 198.000000 MHZ)

        |   |-- emi_clk (flags:0x0, usecount:0, rate: 198.000000 MHZ)

        |   |-- hsi_tx_clk (flags:0x24, usecount:0, rate: 198.000000 MHZ)

        |   |-- enfc_clk (flags:0x0, usecount:0, rate: 19.799999 MHZ)

        |   |    `-- gpmi_io_clk (flags:0x0, usecount:0, rate: 19.799999 MHZ)

        |   |-- usdhc4_clk (flags:0x0, usecount:1, rate: 198.000000 MHZ)

        |   |    `-- gpmi_bch_clk (flags:0x0, usecount:0, rate: 198.000000 MHZ)

        |    `-- usdhc3_clk (flags:0x0, usecount:0, rate: 198.000000 MHZ)

        |       |-- apbh_dma_clk (flags:0x0, usecount:0, rate: 198.000000 MHZ)

        |       |-- gpmi_apb_clk (flags:0x0, usecount:0, rate: 198.000000 MHZ)

        |        `-- gpmi_bch_apb_clk (flags:0x0, usecount:0, rate: 198.000000 MHZ)

         `-- periph_clk (flags:0x0, usecount:4, rate: 528.000000 MHZ)

            |-- axi_clk (flags:0x0, usecount:1, rate: 264.000000 MHZ)

            |   |-- gpu3d_axi_clk (flags:0x0, usecount:0, rate: 264.000000 MHZ)

            |   |-- vpu_clk (flags:0x24, usecount:0, rate: 264.000000 MHZ)

            |   |-- emi_slow_clk (flags:0x0, usecount:0, rate: 132.000000 MHZ)

            |   |-- gpu2d_axi_clk (flags:0x0, usecount:0, rate: 264.000000 MHZ)

            |   |    `-- openvg_axi_clk (flags:0x24, usecount:0, rate: 264.000000 MHZ)

            |   |-- pcie_axi_clk (flags:0x0, usecount:0, rate: 264.000000 MHZ)

            |   |    `-- pcie_clk (flags:0x24, usecount:0, rate: 264.000000 MHZ)

            |    `-- vdo_axi_clk (flags:0x0, usecount:0, rate: 264.000000 MHZ)

            |        `-- vdoa_clk (flags:0x24, usecount:0, rate: 264.000000 MHZ)

            |-- ahb_clk (flags:0x0, usecount:4, rate: 132.000000 MHZ)

            |   |-- sdma_clk (flags:0x0, usecount:0, rate: 132.000000 MHZ)

            |   |-- mx6per1_clk (flags:0x0, usecount:3, rate: 132.000000 MHZ)

            |   |    `-- pl301_mx6qperl_bch (flags:0x0, usecount:0, rate: 132.000000 MHZ)

            |   |-- ipg_clk (flags:0x0, usecount:4, rate: 66.000000 MHZ)

            |   |   |-- spba_clk (flags:0x0, usecount:0, rate: 66.000000 MHZ)

            |   |   |-- iim_clk (flags:0x0, usecount:1, rate: 66.000000 MHZ)

            |   |    `-- ipg_perclk (flags:0x0, usecount:1, rate: 6.000000 MHZ)

            |   |       |-- i2c_clk_0 (flags:0x0, usecount:0, rate: 6.000000 MHZ)

            |   |       |-- i2c_clk_1 (flags:0x0, usecount:0, rate: 6.000000 MHZ)

            |   |       |-- i2c_clk_2 (flags:0x0, usecount:0, rate: 6.000000 MHZ)

            |   |       |-- pwm_clk_0 (flags:0x0, usecount:1, rate: 6.000000 MHZ)

            |   |       |-- pwm_clk_1 (flags:0x0, usecount:0, rate: 6.000000 MHZ)

            |   |       |-- pwm_clk_2 (flags:0x0, usecount:0, rate: 6.000000 MHZ)

            |   |        `-- pwm_clk_3 (flags:0x0, usecount:0, rate: 6.000000 MHZ)

            |   |-- usboh3_clk (flags:0x24, usecount:1, rate: 132.000000 MHZ)

            |   |-- hdmi_iahb_clk (flags:0x0, usecount:0, rate: 132.000000 MHZ)

            |   |-- aips_tz2_clk (flags:0x0, usecount:0, rate: 132.000000 MHZ)

            |    `-- aips_tz1_clk (flags:0x0, usecount:0, rate: 132.000000 MHZ)

             `-- mmdc_ch0_axi_clk (flags:0x0, usecount:5, rate: 528.000000 MHZ)

                |-- gpu3d_core_clk (flags:0x24, usecount:0, rate: 528.000000 MHZ)

                |-- perfmon0_clk (flags:0x0, usecount:0, rate: 528.000000 MHZ)

                |-- perfmon2_clk (flags:0x0, usecount:0, rate: 528.000000 MHZ)

                |-- ipu1_clk (flags:0x24, usecount:1, rate: 264.000000 MHZ)

                |   |-- perfmon1_clk (flags:0x0, usecount:0, rate: 264.000000 MHZ)

                |    `-- ipu1_pixel_clk_1 (flags:0x0, usecount:0, rate: 0.000000 HZ)

                 `-- ipu2_clk (flags:0x24, usecount:0, rate: 264.000000 MHZ)

                    |-- ipu2_pixel_clk_0 (flags:0x0, usecount:0, rate: 0.000000 HZ)

                     `-- ipu2_pixel_clk_1 (flags:0x0, usecount:0, rate: 0.000000 HZ)

Sincerely,Max

[lily_zhang]

Hello, Max:

We enabled the same clock tree on MX6DQ sabreSD board.

  |-- pll5_video_main_clk (flags:0x0, usecount:1, rate: 297.000000 MHZ)

|   |-- ipu1_di_clk_0 (flags:0x24, usecount:1, rate: 148.500000 MHZ)

The pixel clock tree is:

pll5(297MHz) -> 2 divider -> ipu1_di_clk_0(148.5MHz) -> ipu1_pixel_clk_0(148.5MHz)

On the scope,we can see ipu1_di_clk_0 signal quality on clko1 is better than ipu1_pixel_clk_0 at the display panel side.

And, ipu1_pixel_clk_0 signal on MX6DQ SabreSD board is much better than the one on your board.

We saved the snapshot of the scope screen for the two cases in the attachment, for your reference.

Basically we think pll5 clock should be ok, and ipu pixel clock may be impacted by something at the board level. Can you please check?

[MaxChou]

Hi  Ziaoli

I measured the SABRE_SD rev:C2 EVM,

the waveform is like yours,

do you think it will not impact a anolog display(Like VGA) ?

because our design is using DISP0 and add video DAC(THS8135) to get VGA out interface.

Why does "ipu1_pixel_clk_0" have this phenomenon at higher frequency?

Sincerely,Max Chou

[daiane_angolini]

Take a look on imx6 Reference Manual, at page 2232-2235. It may help you.

[MaxChou]

Hi Daiane Angolini

So I should modify "speed field" for DISP_CLK & DISP_DATA0-23 right ?

Below is the unstable clock waveform.

Sincerely,Max Chou

[daiane_angolini]

I´m sorry, but I don´t have enough expertise to help you on this.

Maybe karinavalencia know someone who can help on this issue.