i.mx6 DDR3 64-bit ECC layout

[akohlsmith]

I'm looking at using the i.MX6 in an application that requires ECC.

Specifically I am wondering if there are any layout recommendations for using 16-bit wide DDR3L in an ECC configuration (5 devices). Does the i.mx6 (dual or quad) support fly-by routing, or do I have to route such that the address and control lines are trace-length matched? Are there any issues with using "half" of the 16-bit DDR3L memory module for ECC, or do I have to use 9 8-bit wide devices?

[igorpadykov · Accepted solution]

Hi Andrew

only layout recommendations are given in User Guide below

IMX6DQ6SDLHDG

IMX6DQ6SDLHDG, Hardware Development Guide for i.MX 6Quad, 6Dual, 6DualLite, 6Solo Families of Applications Processors

Processors (all) support fly-by routing.

Regarding "any issues with using "half" of the 16-bit DDR3L memory module for ECC" -

I am not aware of such, just because seems nobody else used "ECC" with i.MX6.

Note. processor does not support memory ECC in hardware.

Best regards

chip

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[akohlsmith]

Thank you very much for your reply; I had expected that the freescale community site would notify me that there was a response, so please forgive my late reply.

I was a little surprised when you stated that no i.MX6 supports ECC; I've been working with a couple of Avnet FAEs and nobody caught this, including myself. This is potentially a deal breaker for us; I need to consult with my peers.

I've got the hardware development guide and it's VERY nice, one of the reasons I'm keen on Freescale is their excellent documentation and support.