We are studying a board based on i.MX53.
We start from the QSB start-r design. We have a question, what is the topology used for the DDR3 memory?
T or fly-by?
Sorry about the delay. I'm checking the MX53 QSB design and yes, the lengths of the DDR traces are not exactly as we recommend. To be honest, I don't know how the constraints were set on that design, but what I can say is: The success or failure of a specific design with these characteristics depends on the DDR operating factors. The guidelines we recommend assure a correct functionality of the DDR no matter its frequency. If the guidelines are not observed, the system has more probability to fail, but it doesn't mean it will fail. I'd recommend you to follow the guidelines so your system is robust enough to handle any possible issue.
I apologize about the confusion with the QSB design, but the guidelines in the UG will help you with signal integrity and good functionality of your system.