Hi all
I have a question about USB Host communication error.
When I tested the USB host, the USB communication stop.
I set the SDIS bit of HW_USBCTRL_USBMODE and it resolved.
So I think the cause is underrun.
Q1.
Is there any registers to inform the occurring the underrun ?
Q2.
Is it the device spec to stop the USB Host when the underrun occurs ?
Ko-hey
Solved! Go to Solution.
Hello,
Below is possible new (non-published) i.MX28 erratum.
ERR006308: USB: HOST controller lock-up issue
Description:
The USB host controller can lock-up when a FIFO under run occurs on a non-32-bit aligned
data buffer. This applies to both the Host controller and OTG controller in host mode.
Workaround:
1. Set Stream Disable bit (SDIS) in the USBMODE register. This will force the controller to
load an entire packet in the FIFO before starting to transmit on the USB bus. Hence, the
FIFO will never underrun. This will somewhat reduce the max bandwidth of the USB since
there will be idle time as the the controller waits for the entire packet to be loaded.
2. Instead of setting SDIS, the FIFO threshold can be increased such that more data will be
in the FIFO before a packet transmit is started. This increases the tolerance to bus latency
and avoid FIFO under run. The Threshold can be increased by using higher values for the
TXTHRESHOLD filed in the TXFILLTUNING register. The default value is 2 bursts (64 bytes
if burst size=8).
Also, please look at the following :
Lock up of USB EHCI controller in i.MX28
Have a great day,
Yuri
------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer
button. Thank you!
Hello,
Below is possible new (non-published) i.MX28 erratum.
ERR006308: USB: HOST controller lock-up issue
Description:
The USB host controller can lock-up when a FIFO under run occurs on a non-32-bit aligned
data buffer. This applies to both the Host controller and OTG controller in host mode.
Workaround:
1. Set Stream Disable bit (SDIS) in the USBMODE register. This will force the controller to
load an entire packet in the FIFO before starting to transmit on the USB bus. Hence, the
FIFO will never underrun. This will somewhat reduce the max bandwidth of the USB since
there will be idle time as the the controller waits for the entire packet to be loaded.
2. Instead of setting SDIS, the FIFO threshold can be increased such that more data will be
in the FIFO before a packet transmit is started. This increases the tolerance to bus latency
and avoid FIFO under run. The Threshold can be increased by using higher values for the
TXTHRESHOLD filed in the TXFILLTUNING register. The default value is 2 bursts (64 bytes
if burst size=8).
Also, please look at the following :
Lock up of USB EHCI controller in i.MX28
Have a great day,
Yuri
------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer
button. Thank you!
Hi
Thank you for information.
Will the errata update to the document ?
If yes, please tell me the schedule.
Is there any registers to inform the occurring the underrun ?
Ko-hey
Hello,
Erratum ERR006308 also affects the i.mx28, but I do not have information about plans
to modify i.MX28 Errata.
Regards,
Yuri.