i.mx 8M Mini: Required voltage rails for MIPI DSI?

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i.mx 8M Mini: Required voltage rails for MIPI DSI?

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adevries
Contributor V

In order to use the MIPI DSI interface on the 8M Mini processor, which pins need to be powered? I see 4 pins that might need to be connected:

VDD_MIPI_1P8, VDD_MIPI_1P2, VDD_MIPI_0P9, and MIPI_VREG_CAP.

To use the MIPI interface, do all of these pins need power? I thought that the 1.2V rail was optional, but I'm not sure.

 

Thanks

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john_phillippe
NXP Employee
NXP Employee

Did you see somewhere that the 1.2V rail is optional?  I can't find any mention of that in the datasheet, reference manual or HW developers guide.  The three supplies you mentioned all need powering and the VREG_CAP needs a 2.2nF (16V) capacitor.

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john_phillippe
NXP Employee
NXP Employee

Did you see somewhere that the 1.2V rail is optional?  I can't find any mention of that in the datasheet, reference manual or HW developers guide.  The three supplies you mentioned all need powering and the VREG_CAP needs a 2.2nF (16V) capacitor.

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adevries
Contributor V

Hi john_phillipe,

 

Thanks for the response. I'm honestly not sure why I thought the 1.2V rail was optional. I may have seen something in the reference manual that talked about a 1.2V internal reference. That, and the fact the evaluation board for the 8M Mini DNP's the capacitor on the 1.2V line and puts a 0 ohm in series (so you can disconnect it from the 1.2V rail?)

 

adevries_0-1614982205998.png

 

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john_phillippe
NXP Employee
NXP Employee

I went down the rabbit hole to get to the bottom of this mystery!

1. There is still a 0.22uF cap on the 1.2V MIPI supply - C244.

2. The i.MX 8M Mini and Nano parts are "pin compatible" and so the compute module design for the Mini was updated to support the Nano.  One of those changes was the C405 and R136 addition.  In the design phase of the Nano there was a plan to add a 1.2V LDO for the VDD_MIPI_1P2 supply pin which would have negated the need for an external supply.  Which is why that option to disconnect that supply pin was added to the EVK.  At some point during design phase the LDO feature was disabled but the EVK was never changed.

3. On the i.MX 8M Plus there IS an LDO that DOES supply VDD_MIPI_1V2.  So that part doesn't require an external 1.2V supply for the MIPI PHY. 

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adevries
Contributor V

Hi john_phillippe,

Thank you very much for looking into this! I appreciate the detail and context this gives me on the 1.2V MIPI supply. So, to summarize: In the design phase of the 8M Mini and Nano, there was a plan at one point to include an internal 1.2V LDO. This is why the option to disconnect 1.2V is seen on the evaluation board. This also probably why some MIPI registers refer to a 1.2V internal LDO in the 8M Mini Reference Manual (see picture below).

adevries_1-1615243607005.png

 

However, neither the 8M Nano nor the 8M Mini have this capability, so to use the MIPI module on these processors you must externally provide 1.2V. 

That all makes sense. I appreciate the context!

 

Looking at the timing diagrams, VDD_MIPI_1P2 should be the last rail to turn on and the first to turn off. Is it acceptable to just connect a 1.2V LDO to NVCC_3V3 and use that to provide the 1.2V rail? The LDO wouldn't be disabled before NVCC_3V3, but when the 3.3V line drops, the 1.2V LDO will stop as well.

 

Thanks!

 

 

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john_phillippe
NXP Employee
NXP Employee

Thanks for that screenshot, I was struggling to find mention of that LDO in the 8M Plus RM - I wasn't using the right search term! 

As for the power sequencing - the 8M Mini datasheet shows a minimum time delay of 0 so tying your MIPI 1.2V LDO off of a 3.3V supply should be fine.

Just to be clear though - you are planning to connect a 3.3V to 1.2V LDO circuit to that NVCC supply which then puts 1.2V out to the VDD_MIPI_1V2 pin?  And you are NOT trying to connect the 3.3V NVCC supply directly to the VDD_MIPI_1V2 pin (which is an error)?  Your wording is a little ambiguous.

 

1,244 Views
adevries
Contributor V

Hi john_phillippe,

Yes, that is correct. Sorry about my wording, I reread it and I definitely could have been clearer. I am planning to use a 1.2V LDO to generate the 1.2V needed for MIPI. 

 

adevries_0-1615316232019.png

 

My only concern with this approach is that the dropout voltage of the LDO means the 1.2V rail would reach 0V before the 3.3V rail does (see attached photos). Is this acceptable?

 

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john_phillippe
NXP Employee
NXP Employee

There is no relationship internally between the NVCC supplies and the MIPI supplies (0.8V/1.2V/1.8V).  In your example above it's more important to ensure that the three MIPI supplies follow the correct power sequencing order - the 1.2V down first, followed by 1.8V then followed by 0.9V.

Just out of curiosity - are you not using the same PMIC (BD71847MWV) as on the EVK?

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adevries
Contributor V

Okay awesome, that's good to know! And no, I'm not using the BD71847MWV on this design. We decided to use the PF8200, which we've used before to power different rails on the 8M Mini. Our first preference was to use the PCA9450AA, but since that part isn't in stock anywhere, and there's a 52 week lead on it, we decided to go with the PF8200 again, and ideally use the same OTP settings we previously used. Which I think will be doable, thanks to your help!

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