i.mx 8M Mini: How long does it take to enter reset?

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i.mx 8M Mini: How long does it take to enter reset?

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adevries
Contributor V

Hello,

 

I am working on integrating a PMIC design with the i.MX 8M Mini, and I am looking for information on the 8M Mini’s power consumption when POR_B is asserted.

In my application, power can be disconnected at any point from the processor, so I want to make sure there is enough hold-up capacitance to keep the PMIC and processor powered for long enough to turn off the voltage rails in the proper order. Whenever power is disconnected, POR_B is asserted and holds the processor in reset. To determine how much capacitance I need, I need to know how much power the processor uses while in reset, as well as how quickly this power consumption is reached after POR_B is asserted.

In my use case, the 8M Mini may be doing a lot of computations and consuming over 2 watts of power. If power is disconnected while this is happening, POR_B is immediately asserted. Once POR_B is asserted, I’m sure the 8M Mini will eventually enter reset mode and consume much less power than active mode, but nothing happens instantly. So, how long will it take to reach the steady-state power consumption of reset mode? If, after POR_B is asserted, the processor continues to consume 2W of power for 100ms before going into reset, I’ll need to include much more capacitance than if it only take 100us from POR_B assertion to go into reset.

Additionally, once POR_B has been asserted, how long does it take for SD3_RST and DRAM_RESET to assert?

 

Thanks!

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Yuri
NXP TechSupport
NXP TechSupport

@adevries 
Hello,

   Please look at my comments below.

1.
  We do not have consumption estimations just for Your
case, when i.MX POR is asserted. Customers can refer to
app note AN12410 (i.MX 8M Mini Power Consumption Measurement)
regarding main use cases and measurement results.

< https://www.nxp.com/docs/en/application-note/AN12410.pdf >

2.
i.MX8Mm DRAM_RESET is output LOW during reset condition.
SD2_RESET and SD1_RESET pins are configured as inputs
with pull down resistors.

What pins is mentioned as SD3_RST in the question?

Regards,
Yuri.

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adevries
Contributor V

Hi Yuri,

1. Understood. Would it be safe to assume the power consumption would be the same or less compared to suspend mode? More importantly, can you give me any idea how long it takes to reach this power consumption? Is it on the order of nanoseconds, microseconds, or milliseconds?

2. We have configured the NAND pins as an SD interface, so when I say SD3_RST, I mean pin P26.

 

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Yuri
NXP TechSupport
NXP TechSupport

@adevries 
Hello,

  I am afraid, we cannot guarantee, that "the power consumption would be the same
or less compared to suspend mode", since the configuration, when POR_B is always
asserted, has not been investigated and considered as one of standard use cases. 

Regards,
Yuri.

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adevries
Contributor V

Hi @Yuri,

Understood. I will do some testing of my own with an evaluation board, and I think that will tell me what I need to know. Thanks for the help.