Hello,
I am currently developing a custom hardware with the i.MX93 family processor. In order to ensure design reliability, I have been looking at the i.MX93 EVK schematics. And when it comes to configure boot config pins, a question arises.
As far as I understand, i.MX93 family processors read four strap pins to boot in a certain mode. Those pins are multiplexed as UART1_TXD, UART2_TCS, SAI1_TXFS and SAI1_TXD. Theese four pins are read after POR_B signal is deasserted and the values are stored. The BB schematics show the following circuit:
MODE1 pin does not have a PU above DIP switch because it is already in the SOM.
The issue with this is that once that theese pins are configured as UARTs and SAI a voltage divider is connected to them (sometimes with 4.7K top resistor and always with the 1K serie and 100K bot resistors).
In case 4.7K resistor is connected, when MPU signal is pulled LOW there is a DC offset at the voltage divider output (0.6v aprox.).
In casi 4.7K resistor is not connected at HIGH level at voltage divider output will be 3.3V minus a little offset (not that much as in the other case).
I have notied that in the BB UART1, UART2 and SAI1 signals are buffered so that at the buffer output the will be a 3.3V HIGH and 0V LOW level.
I have already used bufferes to achieve this goal too (after ensured that the maximum low level is above the DC offset). My question is as follows, if there is a case that I don't use a buffer certain ICs won't recognise the LOW level? Is there a better circuit for the boot pins that avoids this problem?
Thank you in advance,
Gorka.
