We are thinkering around the idea to implement primarly an AES67 solution on top of the new i.MX93, which has very nice feature set for audio applications. The reference manual list the majority of required features, including the media clock regeneration out of PTPv2 and IEEE1722 AVB Layer 2 packets. In our case, we need to use Layer 3 communication and currently prefer AES67 audio transport. If there is no hardware support in the i.MX93 and a pure software solution will not work out, we would like to use an external FPGA/PLL to generate the missing clocks.
Is there a way to create a IEEE1588:2008 (PTPv2) locked reference clock signal out of the i.MX93 application processors?
Chapter 43.4.5.8 "Flexible Pulse-Per-Second Output" of the reference manual talks about a PPS signal, that seem to be configurable to output a 50 MHz PTP reference clock. May that be the solution to feet an external PLL?
