i.MX93 DSI 640x480 Resolution Direct Output

[AlanWen]

Hi, I'm trying to test the DSI interface with a list of resolutions (1080P, 720P, 480P)

As the DSI resolution referenced from: LT9611UXC-demo-board 

The setup of 1080P and 720P worked well to the output as:

// 1920x1080 (Default)
static const struct drm_display_mode lt9611_panel_mode = {
	.clock = 148500,
	.hdisplay = 1920,
	.hsync_start = 1920 + 88,
	.hsync_end = 1920 + 88 + 44,
	.htotal = 1920 + 88 + 44 + 148,
	.vdisplay = 1080,
	.vsync_start = 1080 + 4,
	.vsync_end = 1080 + 4 + 5,
	.vtotal = 1080 + 4 + 5 + 36,
};

// 1280x720
static const struct drm_display_mode lt9611_panel_mode = {
	.clock = 74250,
	.hdisplay = 1280,
	.hsync_start = 1280 + 110,
	.hsync_end = 1280 + 110 + 40,
	.htotal =+ 1280 + 110 + 40 + 220,
	.vdisplay = 720,
	.vsync_start = 720 + 5,
	.vsync_end = 720 + 5 + 5,
	.vtotal = 720 + 5 + 5 + 20,
};

But it came with some format error with 480P, the LT9611UXC chip couldn't recognize the clock sent from IMX93.

// 640x480
static const struct drm_display_mode lt9611_panel_mode = {
	.clock = 25175,
	.hdisplay = 640,
	.hsync_start = 640 + 16,
	.hsync_end = 640 + 16 + 96,
	.htotal = 640 + 16 + 96 + 48,
	.vdisplay = 480,
	.vsync_start = 480 + 10,
	.vsync_end = 480 + 10 + 2,
	.vtotal = 480 + 10 + 2 + 33,
};

Take 720P as an example, a correct sample of LT9611UXC init log well be like:

################## LT9611UX Init Start #################
 FW Version: V5.0.02
 chip id = 170493
 Set To DSI Mode!
 Select PortA As Input
 Set To 4 Lane
 HDCP Disable
 CEC Disable!
 mipi byteclk = 53334
 GetWordCount = 0x0f 0x00
 DSI MIPI FMT: RGB888
 h_act = 1280
 v_act = 720
 v_total = 750
 Do not find a video from the list!!
 pah_act = 1280
 pbh_act = 00
 Htotal_sysclk_num = 557
 Frame_sysclk_num = 417459
 settle = 0x05
 HPD change to High
 Read EDID!
 00  ff  ff  ff  ff  ff  ff  00  5a  63  30  0f  01  01  01  01
 0f  1f  01  03  80  30  1b  78  2e  0b  a5  a7  56  52  9d  26
 10  50  54  bf  ef  80  b3  00  a9  40  a9  c0  95  00  90  40
 81  80  81  40  81  c0  02  3a  80  18  71  38  2d  40  58  2c
 45  00  dd  0c  11  00  00  1e  00  00  00  ff  00  56  54  43
 32  31  31  35  30  30  32  30  31  0a  00  00  00  fd  00  32
 4b  18  52  11  00  0a  20  20  20  20  20  20  00  00  00  fc
 00  56  41  32  32  36  31  20  53  65  72  69  65  73  01  2c
 02  03  23  f1  4d  90  05  04  03  02  12  11  13  14  1e  1d
 1f  01  23  09  7f  07  83  01  00  00  68  03  0c  00  10  00
 20  00  00  02  3a  80  18  71  38  2d  40  58  2c  45  00  dd
 0c  11  00  00  1e  01  1d  80  18  71  1c  16  20  58  2c  25
 00  dd  0c  11  00  00  9e  01  1d  00  72  51  d0  1e  20  6e
 28  55  00  dd  0c  11  00  00  1e  8c  0a  d0  8a  20  e0  2d
 10  10  3e  96  00  dd  0c  11  00  00  18  02  3a  80  d0  72
 38  2d  40  10  2c  45  80  dd  0c  11  00  00  1e  00  00  24
 edidnum = 256

As the chip can recognize the mipi byeclk value, but changing to 640x480 resolution, the log would be like:

################## LT9611UX Init Start #################
 FW Version: V5.0.02
 chip id = 170493
 Set To DSI Mode!
 Select PortA As Input
 Set To 4 Lane
 HDCP Disable
 CEC Disable!
 MIPI PortA WC: 0x00 0x00
 MIPI PortB WC: 0x00 0x00
 MIPI PortA Settle/SOT: 0x1e 0x37 0x1f 0xb8 0x1f 0xb8 0x1a 0xb8
 MIPI PortB Settle/SOT: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
 MIPI PortA PN: 0x55
 MIPI PortB PN: 0x00
 HPD change to High
 Read EDID!
 00  ff  ff  ff  ff  ff  ff  00  5a  63  30  0f  01  01  01  01
 0f  1f  01  03  80  30  1b  78  2e  0b  a5  a7  56  52  9d  26
 10  50  54  bf  ef  80  b3  00  a9  40  a9  c0  95  00  90  40
 81  80  81  40  81  c0  02  3a  80  18  71  38  2d  40  58  2c
 45  00  dd  0c  11  00  00  1e  00  00  00  ff  00  56  54  43
 32  31  31  35  30  30  32  30  31  0a  00  00  00  fd  00  32
 4b  18  52  11  00  0a  20  20  20  20  20  20  00  00  00  fc
 00  56  41  32  32  36  31  20  53  65  72  69  65  73  01  2c
 02  03  23  f1  4d  90  05  04  03  02  12  11  13  14  1e  1d
 1f  01  23  09  7f  07  83  01  00  00  68  03  0c  00  10  00
 20  00  00  02  3a  80  18  71  38  2d  40  58  2c  45  00  dd
 0c  11  00  00  1e  01  1d  80  18  71  1c  16  20  58  2c  25
 00  dd  0c  11  00  00  9e  01  1d  00  72  51  d0  1e  20  6e
 28  55  00  dd  0c  11  00  00  1e  8c  0a  d0  8a  20  e0  2d
 10  10  3e  96  00  dd  0c  11  00  00  18  02  3a  80  d0  72
 38  2d  40  10  2c  45  80  dd  0c  11  00  00  1e  00  00  24
 edidnum = 256

What's wrong with the output of IMX93 DSI in 480P resolution  ? How can I checkout the clock rate ?

Is there anyother way to test the IMX93 DSI direct outputing the 640x480 resolution ?

Please help, thanks in advance.

[AldoG]

Hello,

DId you change anything at device tree or are you using default one?
Also, you may try dump the clocks with the following command:
$ cat /sys/kernel/debug/clk/clk_summary

Best regards/Saludos,
Aldo.

[AlanWen]

Is there any update about this is issue ?