i.MX8XQXP A35 Shareability domains

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i.MX8XQXP A35 Shareability domains

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david_binet
Contributor II

Hi,

I'm currently working on an i.MX8XQXP and I'm not able to find a definition of the shareability domains. From the A35 reference manual, I was able to find this information.

How were those signals set in the i.MX8X implementation? If the outer or inner shareability domain extend beyond the processor, which peripherals are included in each domain? Is there a specific documentation which provide this information ?

Kind Regards,

David 

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igorpadykov
NXP Employee
NXP Employee

Hi David

one can look at

System Controller Firmware 101 - Resource management service 

SCFW Porting Guide included in SCFW Porting Kit


Best regards
igor
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david_binet
Contributor II

Hi Igor,

Thanks for the quick response. I looked at the link and I'm not sure if I understand completely. If the A35 cluster and a peripheral are in the same partition. How should I configure a MMU zone in the DDR for maximum efficiency? Would inner shareable be shared among all components of a partition ? Or would it be outer shareable.

Kind Regards,

David 

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igorpadykov
NXP Employee
NXP Employee

Hi David

could you clarify "MMU zone in the DDR for maximum efficiency" ?

Best regards
igor

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david_binet
Contributor II

Hi  Igor,

Sure I wasn't really clear. For example, I'm working on the ENET and the buffer descriptor are written in DDR by the A35. If i set the MMU zone as cacheable outershareable. Would that configuration insure that a write by the A35 would be seen by the ENET? Or if I do a memory barrier DSB OSHST would that insure that the write is now visible to the ENET?

Kind Regards,

David

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igorpadykov
NXP Employee
NXP Employee

Hi David

yes write by the A35 would be seen by the ENET.

Best regards
igor

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david_binet
Contributor II

Hi Igor,

Thanks for the quick response. Would every peripherals see the write by the A35? If so, what is the difference between a memory barrier on outer shareable and one on the full system DSB ST for example. What about inner shareable would it only be seen between the cores inside the A35 cluster and no peripherals outside the cluster?

Kind Regards,

David

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igorpadykov
NXP Employee
NXP Employee

Hi David

>Would every peripherals see the write by the A35? 

please look at suggested links in my first answer.

At references to resource : SC_R_A53, documentation gives expanations

which peripherals could be seen by A35 and how software configures it.

Regarding " memory barrier on outer shareable and one on the full system DSB ST" -

this applies to arm core operation.  While "shareability domains" as far as I understood your

question refers to concept of " isolating resources from one another" - this is done

using SCU and SCFW : https://community.nxp.com/docs/DOC-341481 

Best regards
igor

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