i.MX8QXP PCie - "phy link never came up" and VDD_PCIE_DIG_1P8_3P3 pin

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i.MX8QXP PCie - "phy link never came up" and VDD_PCIE_DIG_1P8_3P3 pin

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gslm
Contributor I
Hello NXP team,

We're designing a custom board based on the NXP i.MX8QXP reference board (i.MX8QXP-MEK).

In our setup, we're failing to communicate with a Wifi external module using the PCIe interface. Unlike the MEK, however, we use an on-board soldered module, instead of an M.2 card slot

Kernel log messages state an error error in the PHY link stage, and the "phy link never came up" shows up, along with error -110:

 

[    1.424457] ehci-pci: EHCI PCI platform driver
[    1.441283] ohci-pci: OHCI PCI platform driver
[    2.809918] imx6q-pcie 5f010000.pcie: No cache used with register defaults set!
[    2.845346] imx6q-pcie 5f010000.pcie: PCIe PLL is locked.
[    2.860583] imx6q-pcie 5f010000.pcie: iATU unroll: disabled
[    2.866237] imx6q-pcie 5f010000.pcie: Detected iATU regions: 6 outbound, 6 inbound
[    2.873907] imx6q-pcie 5f010000.pcie: host bridge /bus@5f000000/pcie@0x5f010000 ranges:
[    2.889200] imx6q-pcie 5f010000.pcie:       IO 0x007ff80000..0x007ff8ffff -> 0x0000000000
[    2.905010] imx6q-pcie 5f010000.pcie:      MEM 0x0070000000..0x007fefffff -> 0x0070000000
[    2.921022] imx6q-pcie 5f010000.pcie: iATU unroll: disabled
[    2.934114] imx6q-pcie 5f010000.pcie: Detected iATU regions: 6 outbound, 6 inbound
[    3.935037] imx6q-pcie 5f010000.pcie: Phy link never came up
[    3.940769] imx6q-pcie 5f010000.pcie: PHY DEBUG_R0=0x00007e00 DEBUG_R1=0x08200000
[    3.941390] imx6q-pcie: probe of 5f010000.pcie failed with error -110

 

PCIeb node in the device tree is mostly unchanged from the MEK - we've set a fixed lower link speed and a (currently unused) disable-gpio pin:

 

&pcieb{
    compatible = "fsl,imx8qxp-pcie","snps,dw-pcie";
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_pcieb>;
    pinctrl-1 = <&pinctrl_wifi_init>;
    //disable-gpio = <&lsio_gpio1 3 GPIO_ACTIVE_LOW>;
    reset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>;
    clkreq-gpio = <&lsio_gpio4 1 GPIO_ACTIVE_LOW>;
    ext_osc = <1>;
    fsl,max-link-speed = <1>;
    status = "okay";
};

 

 

pinctrl_wifi_init: wifi_initgrp{
      fsl,pins = <
      /* reserve pin init/idle_state to support multiple wlan cards */
      IMX8QXP_SPI2_SCK_LSIO_GPIO1_IO03    0x06000021
      >;
};  

 

 

A notable difference is the VDD_PCIE_DIG_1P8_3P3 pin - we've set it to 1v8 in our custom board. However, the MEK board uses 3v3.

custom boardcustom boardi.MX8QXP-MEKi.MX8QXP-MEK

 

  • Does the VDD_PCIE_DIG_1P8_3P3 voltage change requires a device tree change as well?
  • Could the PHY link issue be caused by and impedance mismatching between module and processor?
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guilhermes
Contributor II

Hello @riteshmpatel, thanks for the reply. We were able to correctly detect the external module after fixing a faulty differential PCB trace in our design.

View solution in original post

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riteshmpatel
NXP TechSupport
NXP TechSupport

Hi @gslm,

I hope you are doing well.

The "Phy link never came up" error comes when the PCI link is not getting up. To debug the same kindly check if the board follows Table 11. PCIe recommendations and Table 27. Trace impedance recommendations of IMX8HWDG document.

Thanks & Regards,
Ritesh M Patel

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guilhermes
Contributor II

Hello @riteshmpatel, thanks for the reply. We were able to correctly detect the external module after fixing a faulty differential PCB trace in our design.

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