I'm currently working on the cortex M4 in the i.MX8QXP. I want to fill both caches of the M4 (Code and System caches) with dirty entries. Once, I know both caches are filled, I want to measure how long it takes to clean an invalidate both caches. To do so, I need to know the cache replacement policy for both caches. I don't find the information in the IMX8QXP reference manual. Is there an algorithm I can use to fill both caches with dirty entries?
From my understanding from previous discussion on this forum the cache linked to the TCM_L will be kind of hard to fill with dirty entries since the memory map for this region looks like this
The memory attributes of TCM_L address region is hardwired as non-cacheable. This means M core skips cache controller when accessing TCM_L or even TCM_U whenever these regions are configured.
Both of the Code cache and System cache are implemented as below:
cache line always in 0x20 address alignment (32-byte in one line)
You would see there are two ways for each cache with the total size of 16KB for each cache part.
So I suggest to fill 16KB address continuous data for other memory instead of TCM, for example OCRAM or DDR.
And in theory this will fully fill the cache line with dirty tags if you don't do a cache clean.
Hope it helps.
The information provided in fsl_cache.c isn't sufficient. From the documentation, I know the L1 data and instruction cache replacement policy of the A35 and also the L2 cache. I'm expecting the same type of information to be provided for both M4 caches.