i.MX8QXP Cortex M4 caches replacement policy

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i.MX8QXP Cortex M4 caches replacement policy

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Contributor II

Hi,

I'm currently working on the cortex M4 in the i.MX8QXP. I want to fill both caches of the M4 (Code and System caches) with dirty entries. Once, I know both caches are filled, I want to measure how long it takes to clean an invalidate both caches. To do so, I need to know the cache replacement policy for both caches. I don't find the information in the IMX8QXP reference manual.  Is there an algorithm I can use to fill both caches with dirty entries?

From my understanding from previous discussion on this forum the cache linked to the TCM_L will be kind of hard to fill with dirty entries since the memory map for this region looks like this

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Kind Regards,

David

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NXP Employee
NXP Employee

Hi david_binet,

The memory attributes of TCM_L address region is hardwired as non-cacheable. This means M core skips cache controller when accessing TCM_L or even TCM_U whenever these regions are configured.

 

Both of the Code cache and System cache are implemented as below:

  • CACHE - 16 KByte size = (256 sets) x (32-byte lines) x (2-way set associative) for both PS and PC cache on CM4.
  • cache line always in 0x20 address alignment (32-byte in one line)

You would see there are two ways for each cache with the total size of 16KB for each cache part.

So I suggest to fill 16KB address continuous data for other memory instead of TCM, for example OCRAM or DDR.

And in theory this will fully  fill the cache line with dirty tags if you don't do a cache clean.

Hope it helps.

 

 

 

Life is not easy!

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NXP TechSupport
NXP TechSupport

david.binet@ca.thalesgroup.com 

Hello,

   I am afraid customers can use only C-functions, provided in the SDK in fsl_cache.c (fsl_cache.h)

to control the caches.

Welcome | MCUXpresso SDK Builder 

Regards,

Yuri.

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Contributor II

Hi Yuri,

The information provided in fsl_cache.c isn't sufficient. From the documentation, I know the L1 data and instruction cache replacement policy of the A35 and also the L2 cache. I'm expecting the same type of information to be provided for both M4 caches. 

Kind Regards,

David

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NXP TechSupport
NXP TechSupport

@david_binet 
Hello,

  "The CM4 subsystem cache uses a single counter to do round robin replacement for the 2-way, set associative cache.

The replacement algorithm is not LRU or round robin by set, it is a single, one bit state for the whole cache."

 

Regards,
Yuri.

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