i.MX8QM: How Cortex-M4 access another cores' LPUART

[michaeltang_ltc]

Hello there,

I'm wondering if it's possible to access each cores' LPUART, said, CM4_0 access CM4_1's LPUART? How to capture/send the message in another core?

I found the base address of M4_0__LPUART and M4_1__LPUART is different, in MIMX8QM6_cm4_core0.h,

• #define CM4_0__LPUART_BASE (0x41220000u)
• #define CM4_1__LPUART_BASE (0x3B220000u)

and in MIMX8QM6_cm4_core1.h, it is

• #define CM4_0__LPUART_BASE (0x37220000u)
• #define CM4_1__LPUART_BASE (0x41220000u)

, but the IRQ number is the same:

• M4_0_LPUART_IRQn = 25
• M4_1_LPUART_IRQn = 25

I though it's possible to access each others UART but the interrupt might be a problem.

[igorpadykov]

Hi Michael

such access is performed using "partition" concept, please check relevant

documentation and SCU APIs on:

System Controller Firmware 101 - Resource management service 

SCFW Porting Kit

Best regards
igor
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[michaeltang_ltc]

Hi Igor,

Thanks for your reply, I thought the SCFW resource partitioning mechanism is providing an access guard for different resources. But how about the M4_x_LPUART_IRQn? They're in the same number in each core. Does the INTMUX of CM4 is used for passing interrupt from CM4_0 to CM4_1? Do you have any suggestion for cross-core-handling of the dedicated interrupt?

Best regards,

Michael Tang

[vinothkumars]

Hi @michaeltang_ltc 

Did you find the solution ?

[igorpadykov]

Hi Michael

for M4 please look at examples in SDK_MIMX8QM_M4

Welcome | MCUXpresso SDK Builder 

Best regards
igor