Hello,
we have a custom board with an MIMX8MQ5DVA with mask set 0N14W. We use that together with a Samsung K4F8E3S4HB-MFCJ LPDDR4. The RAM is running with 800MHz as main frequency and 200MHz for the FREQ1 set point.
The first prototypes of the board worked well and so we started production. Now we have quite some boards where the RAM training fails during U-Boot SPL (about 5 to 10 %) on some boards with a temperature dependency. If I try to train these boards with the "NXP i.MX/Mscale DDR Tool" Version 2.10 for 800MHz and 200MHz I get a fail with the output at the end of the post. The same is true for Version 1.0 that we originally used for the boards. The odd thin is: 800MHz + 334MHz work fine.
My colleague found the erratum e11327 "DDR PHY: LPDDR4 may fail when switching from PHY PLL bypass mode to
PHY PLL Mission mode" for our mask set:
Is it likely that the behavior we see is connected to the erratum? Is there some workarround for it except for using 334MHz? We would really like to get the extra energy saving of the 200MHz.
With kind regards
Christian Mauderer
DDR Tool output with 800MHz + 200MHz:
============ Step 1: DDRPHY Training... ============
---DDR 1D-Training @800Mhz...
[Process] End of CA training
[Process] End of initialization
[Process] End of read enable training
[Process] End of fine write leveling
[Process] End of read DQ deskew training
[Process] End of MPR read delay center optimization
[Process] End of Write Leveling coarse delay
[Process] End of write delay center optimization
[Process] End of read delay center optimization
[Process] End of max read latency training
[Result] PASS
---DDR 1D-Training @200Mhz...
[Process] End of CA training
[Process] End of initialization
[Process] End of read enable training
[Process] End of fine write leveling
[Process] End of MPR read delay center optimization
[Process] End of Write Leveling coarse delay
[Process] End of write delay center optimization
[Process] End of read delay center optimization
[Process] End of max read latency training
[Result] PASS
---DDR 2D-Training @800Mhz...
[Process] End of initialization
PMU: Error: No passing region found for 1 or more lanes. Set hdtCtrl=4 to see passing regions
PMU: ***** Assertion Error - terminating *****
[Result] FAILED
