i.MX8MQ, I.MX8MM and i.MX8MN I2C clock errata

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i.MX8MQ, I.MX8MM and i.MX8MN I2C clock errata

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felixradensky
Contributor IV

Hi,

NXP Linux and u-boot code configure PMIC I2C bus frequency at 400KHz. See for example:

I.MX8MQ: fsl-imx8mq-evk.dts\freescale\dts\boot\arm64\arch - linux-imx - i.MX Linux kernel 

i.MX8MM:fsl-imx8mm-evk.dts\freescale\dts\boot\arm64\arch - linux-imx - i.MX Linux kernel 

i.MX8MN:fsl-imx8mn-evk.dts\freescale\dts\boot\arm64\arch - linux-imx - i.MX Linux kernel 

However i.MX8MQ, i.MX8MM and i.MX8MN errata state the following:

When the I2C module is programmed to operate at the maximum clock speed of 400 kHz (as
defined by the I2C spec), the SCL clock low period violates the I2C spec of 1.3 uS min. The
user must reduce the clock speed to obtain the SCL low time to meet the 1.3us I2C minimum
required. This behavior means the SoC is not compliant to the I2C spec at 400kHz.

Question: Can i.MX8MQ, i.MX8MM and i.MX8MN PMICs safely operate at 100KHz frequency ?

Thanks.

Felix.

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1 Reply

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diegoadrian
NXP Employee
NXP Employee

Hello,

The errata was created for the I2C devices that are the way to restricted in their specifications. In the case of the PIMIC. It could work with the errata without a problem.

The interface is implemented generally following the fast mode definition which supports up to 400 kbits/s operation (exceptions to the standard are noted to be 7-bit only addressing and no support for general call addressing).

Best regards,

Diego.

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