i.MX8MQ: GIC v2 mode?

[bastian_schick]

Hi,

is the legacy mode (ARE == 0) fully supported?

So far, I get it working on a single core, but it seems the SGI/PPI registers exist only once for all core (instead being banked).

The chip errata does not list any issue regarding GIC.

Any tip is appreciated.

[igorpadykov]

Hi Bastian

one can look at  codes gicv3_driver_init() which checks whether the GIC

supports the GICv2 compatibility mode

gicv3_main.c\v3\gic\arm\drivers - imx-atf - i.MX ARM Trusted firmware 

Best regards
igor
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[bastian_schick]

Did you read my question completely?

"is the legacy mode (ARE == 0) fully supported?

So far, I get it working on a single core, but it seems the SGI/PPI registers exist only once for all core (instead being banked).

The chip errata does not list any issue regarding GIC."

I can see that ARE is 0, so legacy mode should be supported. But in the CPU interface exists only once for all cores. Which is wrong. The registers for PPIs and SGIs should be banked. But they are _not_.

Therefore the question if I am just did not find the right address?

BTW: Why link and not just copy the relevant code?