i.MX8MP Wakeup from GPIO and SAI Interrupts in Low Power Mode

[rahul_ms__]

Hi NXP team,

I’m working on low power modes on the i.MX8M Plus.

1. GPIO Wakeup:
   Can any GPIO be used as a wakeup source from Suspend mode, or are only specific GPIOs supported?

2. SAI Wakeup:
   My application requires waking up the A53 core on audio activity.
   Is it possible to wake up the SoC using SAI interrupts (for example, on Rx activity or FIFO ready)?
   If not directly, can the M7 core handle audio input and wake the A53 using MU interrupts?

Thank you in advance!

[Zhiming_Liu]

Hi @rahul_ms__ 

1. The default setting enables the MU interrupt in GIC, the other bit in GPC IMRs. You need find the GPIO bit in IMR referring GPIO interrupt number.

imx-atf/plat/imx/imx8m/imx8mp/imx8mp_lpa_psci.c at lf-6.6.36-2.1.0 · nxp-imx/imx-atf

/*
 * gic's clock will be gated in system suspend, so gic has no ability to
 * to wakeup the system, we need to config the imr based on the irq
 * enable status in gic, then gpc will monitor the wakeup irq
 */
void imx_set_sys_wakeup(unsigned int last_core, bool pdn)
{
	uint32_t irq_mask;
	uintptr_t gicd_base = PLAT_GICD_BASE;

	if (pdn)
		mmio_clrsetbits_32(IMX_GPC_BASE + LPCR_A53_BSC, A53_CORE_WUP_SRC(last_core),
			IRQ_SRC_A53_WUP);
	else
		mmio_clrsetbits_32(IMX_GPC_BASE + LPCR_A53_BSC, IRQ_SRC_A53_WUP,
			A53_CORE_WUP_SRC(last_core));

	/* clear last core's IMR based on GIC's mask setting */
	for (int i = 0; i < IRQ_IMR_NUM; i++) {
		if (pdn)
			/* set the wakeup irq base GIC */
			irq_mask = ~gicd_read_isenabler(gicd_base, 32 * (i + 1));
		else
			irq_mask = IMR_MASK_ALL;

		mmio_write_32(IMX_GPC_BASE + gpc_imr_offset[last_core] + i * 4,
			      irq_mask);
	}

	/* enable the MU wakeup */
	if (imx_is_m4_enabled())
		mmio_clrbits_32(IMX_GPC_BASE + gpc_imr_offset[last_core] + 0x8, BIT(24));
}

2. If the SAI is controlled by M7, you could wakeup A53 by MU.


Best Regards,
Zhiming