Hello,
I want to better understand the limitations of the MIPI_CSI2 interface on the i.MX8MP. As a customer using one of our SoMs featuring this SoC is running into some issues.
The i.MX8MP features two MIPI-CSI interfaces. Reading the Datasheet and the Reference Manual the only limitations mentioned are related to the pixel clock:
For single Camera, MIPI CSI 1 can support up to 400/500 MHz pixel clock in the
Nominal/Overdrive mode.
• For single Camera, MIPI CSI 2 can support up to 277 MHz pixel clock.
• For dual Camera, both MIPI CSI can support up to 266 MHz pixel clock.
We are running into some issues with MIPI CSI 2 with higher resolutions (> 2048 horizontal). From my research this is likely not a limitation of the MIPI CSI interface, but with the ISI.
On the ISI side, I see some limitations of resolutions with a horizontal resolution higher than 2048, specifically on the reference manual, section 13.4 Image Sensing Interface (ISI).
There, it mentions that the line buffers need to be shared to achieve higher resolutions.
It is my understanding that this should not limit the MIPI CSI 2 interface of using higher resolutions, as the pixel link crossbar should allow the data from MIPI CSI 2 to be routed to a channel that has support for chain buffering.
Is this understanding correct? If so, how could this be configured on the device tree when running linux?
Best Regards,
Bruno