i.MX8MM RMII reference clock

[Sasamy]

Hello, NXP team.

We have a custom board based on i.MX8MM, ethernet PHY LAN8720 with RMII connected as on imx8mm_val (TARGET_IMX8MM_DDR3L_VAL)

https://source.codeaurora.org/external/imx/uboot-imx/tree/arch/arm/dts/fsl-imx8mm-ddr3l-val.dts?h=im...

  pinctrl_fec1: fec1grp {
   fsl,pins = <
    MX8MM_IOMUXC_ENET_MDC_ENET1_MDC  0x3
    MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
    MX8MM_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x4000001f
    MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x56
    MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x56
    MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x56
    MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x56
    MX8MM_IOMUXC_ENET_RXC_ENET1_RX_ER 0x56
    MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x56
    MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x56
   >;
  };‍‍‍‍‍‍‍‍‍‍‍‍‍‍

RMII reference clock initialization is also similar to this board

https://source.codeaurora.org/external/imx/uboot-imx/tree/board/freescale/imx8mm_val/imx8mm_val.c?h=...

static int setup_fec(void)
{
 struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
  = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
 /*
 * GPR1 bit 13:
 * 1:enet1 rmii clock comes from ccm->pad->loopback, SION bit for the pad (iomuxc_sw_input_on_pad_enet_td2) should be set also;
 * 0:enet1 rmii clock comes from external phy or osc
 */

 setbits_le32(&iomuxc_gpr_regs->gpr[1],
   IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_SHIFT);
 return set_clk_enet(ENET_50MHZ);
}‍‍‍‍‍‍‍‍‍‍‍‍‍‍

but the reference clock 50 MHz on the pin MX8MM_IOMUXC_ENET_TD2_ENET1_TX_CLK is missing.
I checked the integrity of the circuit by configuring this pin as a gpio output. Therefore, I have two questions:

1 Can anyone confirm that such clocking of the RMII works on i.MX8MM?
2 In which version of u-boot it is known that this clocking scheme works?

Alexander

[igorpadykov · Accepted solution]

Hi Alexander

RMII works on i.MX8MM using

imx8mm_val.c\imx8mm_val\freescale\board - uboot-imx - i.MX U-Boot 

One can try to check define "CONFIG_TARGET_IMX8MM_DDR3L_VAL" 

and CCM_CCGR10, for debugging one can use CCM_CLKO1,2 signal clocks,

referencing to Table 5-1. Clock Root Table, sect.5.1.8.38 PLL

Clock Output for Test Enable and Select Register (CCM_ANALOG_ANAMIX_PLL_MNIT_CTL)

Reference Manual, IOMUXC_GPR_GPR1 register

imx8mm_val.h\configs\include - uboot-imx - i.MX U-Boot 

Best regards
igor
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

[mirceaciocan]

Hello, we have the same PHY, the same software and the same issue. The phy is supposedly feed by the ENET1 50MHz clock via ENET_TD2 pad, in our situation the clock is present at the MCU pad, but the frequency is 125MHz !!!, like the RGMII. Of course the config parameters are set to RMII and also to DDR3. Needless to say that the PHY is not exceedingly happy :(.

Also on the NXP DDR3L validation board schematic, a Realtek PHY is used, that has its own oscillator actually generates the clock in the direction of the MCU (external clock situation).

So my question is, is it possible to generate a 50MHz clock from the MCU to the PHY, I know that vice-versa is possible, but I didn't find a way to change the output frequency of the clock, only on how to enable or disable it in different modes via the CCM_CCGR10.

In the data sheet it says it's possible, but no example is given in the Reference Manual or anywhere else that I could find:

Used as RMII clock and RGMII data, there are two RGMII clock schemes.
• MAC generate output 50M reference clock for PHY, and MAC also use this 50M clock.
• MAC use external 50M clock.

Could you please tell me how to actually do it that the output frequency is 50MHz ?

Many thanks for your support,

Mircea

[kl4m4]

Same SOC here, different PHY (KSZ8081RNB). Cannot get RMII output 50MHz clock to PHY. When I manually set bit13 in IOMUXC_GPR_GPR1:

devmem2 0x30340004 word 0x2000

I get a clock on PAD_ENET_TD2, but instead of 50MHz, I get 125MHz.

Accepted solution in this thread involves fiddling with u-boot source code. I do not need ethernet during u-boot. Is there a way to fix this just in device tree? So far what I got:

fec1: ethernet@30be0000 { 
compatible = "fsl,imx8mm-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
reg = <0x30be0000 0x10000>; 
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 
clocks = <&clk IMX8MM_CLK_ENET1_ROOT>, 
<&clk IMX8MM_CLK_ENET1_ROOT>, 
<&clk IMX8MM_CLK_ENET_TIMER>, 
<&clk IMX8MM_CLK_ENET_REF>, 
<&clk IMX8MM_CLK_ENET_PHY_REF>; 
clock-names = "ipg", "ahb", "ptp", 
"enet_clk_ref", "enet_out"; 
assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>, 
<&clk IMX8MM_CLK_ENET_TIMER>, 
<&clk IMX8MM_CLK_ENET_REF>, 
<&clk IMX8MM_CLK_ENET_PHY_REF>; 
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>, 
<&clk IMX8MM_SYS_PLL2_100M>, 
<&clk IMX8MM_SYS_PLL2_125M>, 
<&clk IMX8MM_SYS_PLL2_50M>; 
assigned-clock-rates = <0>, <0>10m, <125000000>, <50000000>; 
fsl,num-tx-queues = <3>; 
fsl,num-rx-queues = <3>; 
nvmem-cells = <&fec_mac_address>; 
nvmem-cell-names = "mac-address"; 
nvmem_macaddr_swap; 
stop-mode = <&gpr 0x10 3>; 
fsl,wakeup_irq = <2>; 
status = "disabled"; 
}; 

&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rmii"; /* KSZ8081RNB works in RMII mode */
phy-handle = <&ethphy0>;
phy-reset-gpios = <&gpio1 0 0>; /* GPIO1_0 */
fsl,magic-packet;
max-speed = <100>;
status = "okay";

mdio {
#address-cells = <1>;
#size-cells = <0>;

ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
};
};
};   

Where should I look next?

[Jamier]

Did you resolve this. I too see 125MHz instead of the expected 50MHz

[Sasamy]

Hi Igor.

Thanks for the confirmation. It looks like we missed something when adapting u-boot.

Alexander

[sunil_embex]

Hi,

I am facing the same issue so can you please what was the issue ?

Your help shall be greatly appreciated

Regards,

Paul

[emptyfridge]

Hi Guys,

Here are my changes in u-boot imx_v2019.04_4.19.35_1.1.0.

@@ -60,24 +60,18 @@
 		};
 
 		pinctrl_fec1: fec1grp {
-			fsl,pins = <
-				MX8MM_IOMUXC_ENET_MDC_ENET1_MDC		0x3
-				MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO	0x3
-				MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3	0x1f
-				MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2	0x1f
-				MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1	0x1f
-				MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0	0x1f
-				MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3	0x91
-				MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2	0x91
-				MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1	0x91
-				MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0	0x91
-				MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC	0x1f
-				MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC	0x91
-				MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
-				MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
-				MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11	0x116
-				MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12	0x116
-			>;
+				      fsl,pins = <
+					      MX8MM_IOMUXC_ENET_MDC_ENET1_MDC  0x3
+					      MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
+					      MX8MM_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x4000001f
+					      MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x56
+					      MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x56
+					      MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x56
+					      MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x56
+					      MX8MM_IOMUXC_ENET_RXC_ENET1_RX_ER 0x56
+					      MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x56
+					      MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x56
+					      >;
 		};
 
 		pinctrl_flexspi: flexspigrp {
@@ -402,7 +396,7 @@
 &fec1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_fec1>;
-	phy-mode = "rgmii-id";
+	phy-mode = "rmii";
 	phy-handle = <&ethphy0>;
 	fsl,magic-packet;
 	status = "okay";
@@ -414,9 +408,6 @@
 		ethphy0: ethernet-phy@0 {
 			compatible = "ethernet-phy-ieee802.3-c22";
 			reg = <0>;
-			at803x,led-act-blind-workaround;
-			at803x,eee-okay;
-			at803x,vddio-1p8v;
 		};
 	};
 };
--- a/board/xxxx/port_core/port_core.c
+++ b/board/xxxx/port_core/port_core.c
@@ -161,25 +161,15 @@ static int setup_fec(void)
 {
 	struct iomuxc_gpr_base_regs *gpr =
 		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+	/* Use 50M anatop REF_CLK1 for ENET1, not from external */
+	setbits_le32(&gpr->gpr[1],
+		BIT(IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_SHIFT));
 
-	setup_iomux_fec();
-
-	/* Use 125M anatop REF_CLK1 for ENET1, not from external */
-	clrsetbits_le32(&gpr->gpr[1],
-			IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK, 0);
-	return set_clk_enet(ENET_125MHZ);
+	return set_clk_enet(ENET_50MHZ);
 }
 
 int board_phy_config(struct phy_device *phydev)
 {
-	/* enable rgmii rxc skew and phy mode select to RGMII copper */
-	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
-	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
-
-	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
-	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
-	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
-	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
 
 	if (phydev->drv->config)
 		phydev->drv->config(phydev);
diff --git a/include/configs/port_core.h b/include/configs/port_core.h
index 79a29ec222..5eb375886e 100644
--- a/include/configs/port_core.h
+++ b/include/configs/port_core.h
@@ -89,7 +89,7 @@
 #define CONFIG_ETHPRIME                 "FEC"
 
 #define CONFIG_FEC_MXC
-#define CONFIG_FEC_XCV_TYPE             RGMII
+#define CONFIG_FEC_XCV_TYPE             RMII
 #define CONFIG_FEC_MXC_PHYADDR          0
 #define FEC_QUIRK_ENET_MAC
 

and changes in kernel devtree:

+++ b/arch/arm64/boot/dts/freescale/imx8mm-port-core.dtsi
@@ -119,22 +119,19 @@
 	port-core {
 		pinctrl_fec1: fec1grp {
 			fsl,pins = <
-				MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3	/* AC27  ENET_MDC */
-				MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3	/* AB27  ENET_MDIO */
-				MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f	/* AF25  ENET_TD3 */
-				MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f	/* AG25  ENET_TD2 */
-				MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f	/* AF26  ENET_TD1 */
-				MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f	/* AG26  ENET_TD0 */
-				MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91	/* AC26  ENET_RD3 */
-				MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91	/* AD26  ENET_RD2 */
-				MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91	/* AD27  ENET_RD1 */
-				MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91	/* AE27  ENET_RD0 */
-				MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f	/* AG24  ENET_TXC */
-				MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91	/* AE26  ENET_RXC */
-				MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91	/* AF27  ENET_RX_CTL */
-				MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f	/* AF24  ENET_TX_CTL */
-				MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11		0x6	/* AC10  GPIO1_IO11  ETH_RESET~ */
-				MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12		0x6	/* AB10  GPIO1_IO12  ETH_INT_PWDN~ */
+				MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3		/* AC27  ENET_MDC */
+				MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23		/* AB27  ENET_MDIO */
+				MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x56	/* AF26  ENET_TD1 */
+				MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x56	/* AG26  ENET_TD0 */
+				MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x56	/* AD27  ENET_RD1 */
+				MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x56	/* AE27  ENET_RD0 */
+				MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x56	/* AE26  ENET_RXC */
+				MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x56
+					/* AF27  ENET_RX_CTL */
+				MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x56
+					/* AF24  ENET_TX_CTL */
+				MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x6		/* PHY Reset GPIO1_IO11 */
+				MX8MM_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x4000001f	/* Refclock from PHY */
 			>;
 		};
 
@@ -812,9 +809,10 @@
 &fec1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_fec1>;
-	phy-mode = "rgmii-id";
+	phy-mode = "rmii";
 	phy-handle = <&ethphy0>;
 	fsl,magic-packet;
+	phy-reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
 	status = "okay";
 
 	mdio {
@@ -824,11 +822,6 @@
 		ethphy0: ethernet-phy@0 {
 			compatible = "ethernet-phy-ieee802.3-c22";
 			reg = <0>;
-			ti,rx-internal-delay = <DP83867_RGMIIDCTL_3_75_NS>;
-                        ti,tx-internal-delay = <DP83867_RGMIIDCTL_3_75_NS>;
-                        ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
-			ti,dp83867-rxctrl-strap-quirk;
-			max-speed = <100>;
 		};
 	};
 };
-- 
2.20.1


--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -1082,8 +1082,8 @@
 						  <&clk IMX8MM_CLK_ENET_TIMER>;
 				assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
 							 <&clk IMX8MM_SYS_PLL2_100M>,
-							 <&clk IMX8MM_SYS_PLL2_125M>;
-				assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
+							 <&clk IMX8MM_SYS_PLL2_50M>;
+				assigned-clock-rates = <0>, <0>, <50000000>, <100000000>;
 				fsl,num-tx-queues = <3>;
 				fsl,num-rx-queues = <3>;
 				nvmem-cells = <&fec_mac_address>;
-- 
2.20.1

reset-gpios moved to mdio:

--- a/arch/arm64/boot/dts/freescale/imx8mm-port-core.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-port-core.dtsi
@@ -812,8 +812,7 @@
        phy-mode = "rmii";
        phy-handle = <&ethphy0>;
        fsl,magic-packet;
-       phy-reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
-       phy-reset-duration = <200>;
+       //phy-reset-duration = <200>;
        status = "okay";
 
        mdio {
@@ -824,6 +823,9 @@
                        compatible = "ethernet-phy-ieee802.3-c22";
                        reg = <0>;
                        smsc,disable-energy-detect;
+                       reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
+                       reset-assert-us = <10000>;
+                       reset-deassert-us = <1000>;
                };

with the assert time I'm really not sure. I saw a lot of different configs regarding this.

with this we got the LAN8720 running so far.

But now it runs not stable...

If some one has a stable INIT sequence for the LAN8720 would be great.

If already moved the reset-gpio from fec to mdio section because otherwise the fec_main phy_reset will not work. And if the fec comes up it disables and re-enables the clock 50MHz and after that LAN8720 needs a reset as far as I know. If the reset-gpios is configured in fec area, RST pin is not moving. Therefore it is now in mdio section. But still the LAN8720  does not come up stable. I have Link up/down... or sometimes not even a link at all. Any hints on that ?

[Johnli]

pls check i.MX8MM RMII TXC OUTPUT - NXP Community