Dear NXP Team,
We are integrating the MT53E2G32D4DE-046 AIT:C LPDDR4 memory (8 GB) on our custom board based on the i.MX8M Mini (i.MX8MM) processor.
We have already generated the RAM timing file using the NXP-provided DDR Tool.
Could you kindly help us with official documentation or guidance on:
Supporting 8 GB RAM with i.MX8MM
Any required changes in U-Boot, kernel, and device tree
Reserved memory or address mapping considerations
Addressing constraints (VA/PA) we should be aware of
Any caveats or errata for larger DRAM configurations
We appreciate your support on this.
Best regards,
Yogesh
