Greetings all,
I have scoured the forum for a clear answer and it looks like there are multiple answers to the same question for different SoC's so I am hoping this post can clear it up once and for all for the 8M series.
With regards to the i.MX8M Mini Dual and Quad, is it possible to use the 4-lane MIPI CSI-2 to run two dual-lane CMOS sensors simultaneously without an FPGA between the cameras and SoC?
The question really boils down to whether or not we can pipe the separate dual-lane image sensors to the chip and set up virtual channels via the driver to manage the images separately. Looking through the DRM, it's clear there are 4-lanes available, but it's not clear as to whether or not chipset has the appropriate IPU structure to handle multiple video streams nor is it clear how to handle the clocking of the two sensors.
Has anyone successfully done this?
Note: Our goal would be to NOT use usb and/or PCIe for the secondary camera as they will be occupied with other peripherals and we would like to use the same connectors/hardware.
I appreciate the support!
(Note: OPs question was "solved", but the follow-on was not https://community.nxp.com/t5/i-MX-Processors/Multiple-Cameras-on-iMX8M-Mini/m-p/1022287 )
