i.MX8M+ eth vlan priority, queues & core isolation?

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i.MX8M+ eth vlan priority, queues & core isolation?

502 Views
dav1
Contributor V

Trying to find more details around the frame classification (see from manual below)

Can I for instance filter so that time-sensitive ends up in its own buffer and IRQ,
thus allowing core-isolation so TSN/AVB traffic could be tied to the M7 while L3 traffic is passed to the A53?

 

screenshot_2023-01-02_at_15.28.30.png

 

Would also like some guidance to either code or more in-depth documentation for the two different PHY's in the imx8plus, there are obviously two variants of the IP's used for phy0 vs phy1. I'd like to understand
- what features are supported on each
- more details how fifo's/queues and irq's are segmented

 

thanks

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dav1
Contributor V

reminder to reply

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dav1
Contributor V

I noted in the gen avb examples, it seems hardcoded to use the software ptp rather than the hw feature in the 'tsn phy'. any plans to support both?

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jimmychan
NXP TechSupport
NXP TechSupport

There are two ethernet ports on i.MX8MP. One is normal ENET port, another one is EQOS which support TSN.

Two Ethernet controllers, capable of simultaneous operation
• One Gigabit Ethernet controller with support for EEE, Ethernet AVB
and IEEE1588
• One Gigabit Ethernet controller with support for TSN, EEE, Ethernet AVB
and IEEE1588

 

FYI. AVB/TSN demo.

https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/AVB-TSN-demo-on-i-MX8MP/ta-p/1123791

 

GenAVB/TSN Stack Evaluation User Guide

https://www.nxp.com.cn/docs/en/user-guide/GENAVBTSNUG.pdf

 

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