Trying to find more details around the frame classification (see from manual below)
Can I for instance filter so that time-sensitive ends up in its own buffer and IRQ,
thus allowing core-isolation so TSN/AVB traffic could be tied to the M7 while L3 traffic is passed to the A53?
Would also like some guidance to either code or more in-depth documentation for the two different PHY's in the imx8plus, there are obviously two variants of the IP's used for phy0 vs phy1. I'd like to understand
- what features are supported on each
- more details how fifo's/queues and irq's are segmented
There are two ethernet ports on i.MX8MP. One is normal ENET port, another one is EQOS which support TSN.
Two Ethernet controllers, capable of simultaneous operation
• One Gigabit Ethernet controller with support for EEE, Ethernet AVB and IEEE1588
• One Gigabit Ethernet controller with support for TSN, EEE, Ethernet AVB and IEEE1588
FYI. AVB/TSN demo.
GenAVB/TSN Stack Evaluation User Guide