Hi Arthur,
Sorry. I didn't understood following explanation
"The USB controller exchanges data with cores and other bus masters through a buffers assigned in shared memory."
Does this mean USB Host controllers are always accessible by both M4 and A53 cores? I did following experiments on u-boot and still doesn't understand it fully.
Memory mapped address of Master assignment register for A53, M4, USB1 and 2 are following,
RDC_MDA0 - 0x303d0200
RDC_MDA1 - 0x303d0204
RDC_MDA19 - 0x303d024c
RDC_MDA20 - 0x303d0250
Using UBoot memory write commands, I assigned USB1 and USB2 to domain 1. By default, A53 and M4 are in domain zero. Then I executed "usb start" command to see whether A53 still able to access USB Host. It is working fine. Following are the corresponding serial console snapshot,
=> md 0 c
303d0200: 00000000 00000000 00000000 00000000 ................
303d0210: 00000000 00000000 00000000 00000000 ................
303d0220: 00000000 00000000 00000000 00000000 ................
=>
303d0230: 00000000 00000000 00000000 00000000 ................
303d0240: 00000000 00000000 00000000 00000001 ................
303d0250: 00000001 00000000 00000000 00000000 ................
=> usb start
starting USB...
USB0: Register 2000140 NbrPorts 2
Starting the controller
USB XHCI 1.10
USB1: Register 2000140 NbrPorts 2
Starting the controller
USB XHCI 1.10
scanning bus 0 for devices... 1 USB Device(s) found
scanning bus 1 for devices... 3 USB Device(s) found
scanning usb for storage devices... 0 Storage Device(s) found
=>
I am facing a specific problem when loading M4 RTOS binary from u-boot. It is USB Host application and port status change interrupts are not getting triggered to M4 code when loaded via u-boot. It works fine, when loaded via JTAG. So I am kind of sure that since XHCI controllers are accessible from U-Boot, thats why M4 is not getting XHCI related events and interrupts.
Best Regards,
Dilip