Hi,
I am currently working on a custom board using the i.MX8M Quad (MIMX8MQ6CVAHZAB). Due to the discontinuation of the LPDDR4 we were using, we replaced it with another LPDDR4 of the same capacity. The previous LPDDR4 worked well, but the replacement is failing during DDR Training.
The previously used memory was MT53E768M32D4DT-053 AIT E, and the new one is MT53E768M32D2ZW-046 AITC. According to Micron’s EOL document, they are listed as compatible with each other, but does the i.MX8M Quad (MIMX8MQ6CVAHZAB) not support the new one?
As I mentioned earlier, MT53E768M32D4DT-053 AIT E passes the DDR test and boots the kernel without any issues, but MT53E768M32D2ZW-046 AITC fails from the DDR test stage.
<MICRON EOL>
<MT53E768M32D4DT-053 AIT:E DDR Calibration TEST success>
<MT53E768M32D2ZW-046 AIT:C DDR Calibration TEST FAIL>
The DDR TOOL log is as follows.
Downloading file 'bin\lpddr4_train1d_string_v201709.bin' ..Done
Downloading file 'bin\lpddr4_train2d_string_v201709.bin' ..Done
Downloading file 'bin\lpddr4_imem_1d_v201709.bin' ..Done
Downloading file 'bin\lpddr4_dmem_1d_v201709.bin' ..Done
Downloading file 'bin\lpddr4_imem_2d_v201709.bin' ..Done
Downloading file 'bin\lpddr4_dmem_2d_v201709.bin' ..Done
Downloading IVT header...Done
Downloading file 'bin\m850_ddr_stress_test.bin' ...Done
Download is complete
Waiting for the target board boot...
********Found PMIC PF0100**********
*************************************************************************
*************************************************************************
*************************************************************************
MX8 DDR Stress Test V3.30
Built on Jan 12 2023 16:36:46
*************************************************************************
Waiting for board configuration from PC-end...
--Set up the MMU and enable I and D cache--
- This is the Cortex-A53 core
- Check if I cache is enabled
- Enabling I cache since it was disabled
- Push base address of TTB to TTBR0_EL3
- Config TCR_EL3
- Config MAIR_EL3
- Enable MMU
- Data Cache has been enabled
- Check system memory register, only for debug
- VMCR Check:
- ttbr0_el3: 0x91d000
- tcr_el3: 0x2051c
- mair_el3: 0x774400
- sctlr_el3: 0xc01815
- id_aa64mmfr0_el1: 0x1122
- MMU and cache setup complete
*************************************************************************
ARM clock(CA53) rate: 800MHz
DDR Clock: 1600MHz
============================================
DDR configuration
DDR type is LPDDR4
Data width: 32, bank num: 8
Row size: 16, col size: 10
One chip select is used
Number of DDR controllers used on the SoC: 1
Density per chip select: 1536MB
Density per controller is: 1536MB
Total density detected on the board is: 1536MB
============================================
MX8M: Cortex-A53 is found
*************************************************************************
============ Step 1: DDRPHY Training... ============
---DDR 1D-Training @1600Mhz...
PMU: Error: CA Training Failed.
PMU: ***** Assertion Error - terminating *****
[Result] FAILED
I’ve also attached the RPA document I created and the LPDDR4 datasheet. I would appreciate your help. Thank you.
