i.MX8M Plus DDR4 pin swap rules

[yamamo10]

I am designing a DDR4 connection circuit for the i.MX 8M Plus
(part number: MIMX8ML8CVNKZAB) and am considering pin swapping for routing.

The IMX8MP Hardware Development Guide does not clearly specify
DDR4 pin swapping limitations (for example, bit or nibble-level constraints).

Would it be acceptable to refer to the DDR4 design checklist in AN5097
for i.MX 8M Plus DDR4 designs?

AN5097 states that “bit-swapping across two nibbles is not allowed.”
Does this restriction also apply to the i.MX 8M Plus DDR4 interface,
even if the DQS is not crossed?

Thank you.

[pengyong_zhang]

Hi @yamamo10 

Our document team is adding the DDR4 section to the documentation and will update it before March.

B.R

[pengyong_zhang]

Hi @yamamo10 

There is no problem about "bit swapping across two nibbles within the same byte" of i.MX8MP.

AN5097 is not about i.MX series products.

 

B.R

[yamamo10]

Thank you for the clarification.

I understand that this DDR4 guideline document applies to Layerscape and QorIQ devices,
and that for i.MX parts we should follow i.MX-specific board layout guideline documents.

However, for the i.MX 8M Plus (MIMX8ML8CVNKZAB), we could not find a document that provides
sufficient and concrete DDR4 layout guidance, such as:

- Explicit DDR4 pin / byte / nibble swapping rules
- Detailed routing constraints for DDR4 (length matching, impedance, topology, etc.)
- Any reference designs or layout examples using DDR4 with i.MX 8M Plus

The i.MX8MP Hardware Development Guide and Reference Manual mention DDR4 support,
but do not clearly describe the allowable pin-swapping rules or detailed PCB layout constraints.

Could you please advise:
- Which specific NXP document should be considered authoritative for DDR4 layout on i.MX 8M Plus?
- Or whether it is acceptable to refer to AN5097 (DDR4 Design Checklist) as a guideline,
even though it is not explicitly stated to apply to i.MX 8M Plus?

Any clarification would be greatly appreciated.

[pengyong_zhang]

Hi @yamamo10 

There is no fix rule about your DRAM connection circuit. you only need to make sure that only in one Byte can use bit swap. Do not bit swap between different byte.

B.R

[yamamo10]

Thank you for the clarification.

Based on the IMX8MPHDG and your explanation, I understand that for i.MX 8M Plus DDR4, the DDR4 pin-swap rule is defined at the byte level, and that bit swapping is allowed within the same byte, but not across different bytes.

Since there is no explicit nibble-level restriction described for i.MX 8M Plus (unlike AN5097), we plan to allow bit swapping across two nibbles within the same byte as a design decision.