In our current project using iMX8M Plus, we need to use both MIPI-CSI2 ports connected to an ADV7481 chip, one for HDMI (already working) and another for Analog input.
We managed to properly build both video pipelines in v4l2 by fixing some issues in imx8-mipi-csi2-sam.c file.
Streaming on HDMI pipeline is working properly but there are no frames detected on the Analog pipeline.
This issue seems similar to one we had a few month ago with HDMI and which was related to HS_SETTLE settings.
The measured mipi clk signal at the MIPI-CSI2 input port is 100 MHz and verification has been done that there is some activity on data lane.
Different hs_settle settings from 1 to 31 have been tested without success.
See attached MIPI-DPHY status logs.
CSIS_DPHYSTATUS toggles between 0xe2 and 0xf1 but the expected value should be 0xe0 (we only use 1 lane on the second MIPI-CSI2 port).
Can you please help us to find what can cause this issue here. Are the settings different on the second MIPI-CSI2 port ?
