i.MX8M Nano DDR Calibration for single-die 16Gb density not supported by MX8M_Nano_LPDDR4_RPA_v5.xls

[timharvey]

Greetings,

We have a board designed with the iMX8M Nano with a single x16 LPDDR4 16Gb single-die chip (Micron MT53E1G16D1). This chip has 1 die thus 1 chip select, 3 banks, 17 rows, 10 cols. However when I configure this in the MX8M_Nano_LPDDR4_RPA_v5 spreadsheet the resulting configuration in the mscale_ddr_tool_v3.20 shows 16 rows and half the memory and the resulting dram timing does not work.

I suspect something in the spreadsheet register calculation is wrong.

*************************************************************************
ARM clock(CA53) rate: 1500MHz
DDR Clock: 1600MHz

============================================
DDR configuration
DDR type is LPDDR4
Data width: 16, bank num: 8
Row size: 16, col size: 10
One chip select is used
Number of DDR controllers used on the SoC: 1
Density per chip select: 1024MB
Density per controller is: 1024MB
Total density detected on the board is: 1024MB
============================================

MX8M-nano: Cortex-A53 is found

The above 'should' show 'Row size: 17', and density of 2048MB.

Please advise.

[decastro_25]

Hi @timharvey ,

I've also on mind do a prototype board with IMX8MN and the same LPDDR4 than you. In the post hasn't exist a correct or valid response, so I'm not sure if finally did you get the DDR work in your design. 

Could you confirm me if finally did you get it work? And if you've been succeded, how did you configure the DDR Stress tool and the RPA excel? Did you upload the files to the u-boot folder and finally boot the board?

I'll be waiting your news asap.

Thanks in advance,

[timharvey]

I got this working by adding 'memory set 0x3D40021C 32 0x00000007 #DDRC_ADDRMAP7' to the RPAv5 spreadsheet to properly set the DDRC_ADDRMAP7 register. The register is defined in the IMX8MNRM. It is not a 'supported' configuration meaning Micron nore NXP validated it but that doesn't mean it does not work (works fine!).

It is unfortunate that NXP does not want to validate this configuration especially considering that with the chip shortage you can not get the only DRAM part they validated and recommend for this size configuration.

Tim

[timharvey]

It seems the issue is that the MX8M_Nano_LPDDR4_RPA_v5 spreadsheet does not configure ADDRMAP7-11 registers. Adding them to the configuration file fed to the mscale ddr tool ended up properly configuring DRAM.

I assume NXP needs to update all the RPA spreadsheets to support configuring ADDRMAP7+ for additional row addressing.

Tim

[igorpadykov]

Hi Tim 

additional details were sent via mail.

Best regards
igor

[igorpadykov]

Hi Tim 

additional details were sent via mail.

Best regards
igor

[igorpadykov]

Hi Tim 

unfortunately i.MX8M Nano does not support lpddr4 devices with 17-row addresses, sorry.

Best regards
igor

[timharvey]

Igor,

Why do you say 17-row addressing is not supported on the Nano? I originally thought this as well but the i.MX8M Nano reference manual section 9.2.3.1.68 shows ADDRMAP7 configuration for b16 and b17. Forcing this value into the configuration for the mscale ddr tool did show the proper DRAM configuration and stress test passes:

===================hardware_init=====================

********Found PMIC BD718XX**********
hardware_init exit

*************************************************************************

*************************************************************************

*************************************************************************
MX8 DDR Stress Test V3.20
Built on Feb 23 2021 13:49:21
*************************************************************************

Waiting for board configuration from PC-end...

--Set up the MMU and enable I and D cache--
- This is the Cortex-A53 core
- Check if I cache is enabled
- Enabling I cache since it was disabled
- Push base address of TTB to TTBR0_EL3
- Config TCR_EL3
- Config MAIR_EL3
- Enable MMU
- Data Cache has been enabled
- Check system memory register, only for debug

- VMCR Check:
- ttbr0_el3: 0x97d000
- tcr_el3: 0x2051c
- mair_el3: 0x774400
- sctlr_el3: 0xc01815
- id_aa64mmfr0_el1: 0x1122

- MMU and cache setup complete

*************************************************************************
ARM clock(CA53) rate: 1500MHz
DDR Clock: 1600MHz

============================================
DDR configuration
DDR type is LPDDR4
Data width: 16, bank num: 8
Row size: 17, col size: 10
One chip select is used
Number of DDR controllers used on the SoC: 1
Density per chip select: 2048MB
Density per controller is: 2048MB
Total density detected on the board is: 2048MB
============================================

MX8M-nano: Cortex-A53 is found

*************************************************************************

============ Step 1: DDRPHY Training... ============
---DDR 1D-Training @1600Mhz...
[Process] End of CA training
[Process] End of initialization
[Process] End of read enable training
[Process] End of fine write leveling
[Process] End of read DQ deskew training
[Process] End of MPR read delay center optimization
[Process] End of Write Leveling coarse delay
[Process] End of write delay center optimization
[Process] End of read delay center optimization
[Process] End of max read latency training
[Result] PASS
---DDR 1D-Training @200Mhz...
[Process] End of CA training
[Process] End of initialization
[Process] End of read enable training
[Process] End of fine write leveling
[Process] End of MPR read delay center optimization
[Process] End of Write Leveling coarse delay
[Process] End of write delay center optimization
[Process] End of read delay center optimization
[Process] End of max read latency training
[Result] PASS
---DDR 1D-Training @50Mhz...
[Process] End of CA training
[Process] End of initialization
[Process] End of read enable training
[Process] End of fine write leveling
[Process] End of MPR read delay center optimization
[Process] End of Write Leveling coarse delay
[Process] End of write delay center optimization
[Process] End of read delay center optimization
[Process] End of max read latency training
[Result] PASS
---DDR 2D-Training @1600Mhz...
[Process] End of initialization
[Process] End of 2D read delay/voltage center optimization
[Process] End of 2D write delay/voltage center optimization
[Result] PASS

============ Step 2: DDR memory accessing... ============
Verifying DDR frequency point0@1600MHz.......Pass
Verifying DDR frequency point1@200MHz.......Pass
Verifying DDR frequency point2@50MHz.......Pass
[Result] OK

============ Step 3: DDR parameters processing... ============
[Result] Done

Success: DDR Calibration completed!!!
'lpddr4_timing.c' is created!
DDR Stress Test Iteration 1
--------------------------------
--Running DDR test on region 1--
--------------------------------

t0.1: data is addr test
....
t0.2: row hop read test
...

t1: memcpy SSN armv8_x32 test
....
t2: byte-wise SSN armv8_x32 test
..
t3: memcpy pseudo random pattern test
....................................................................
t4: IRAM_to_DDRv1 test
...

t5: IRAM_to_DDRv2 test
--------------------------------
--Running DDR test on frequency point1@200MHz--
--------------------------------

t0.1: data is addr test
....
t0.2: row hop read test
...

t1: memcpy SSN armv8_x32 test
....
t2: byte-wise SSN armv8_x32 test
..
t3: memcpy pseudo random pattern test
....................................................................
t4: IRAM_to_DDRv1 test
...

t5: IRAM_to_DDRv2 test
--------------------------------
--Running DDR test on frequency point2@50MHz--
--------------------------------

t0.1: data is addr test
....
t0.2: row hop read test
...

t1: memcpy SSN armv8_x32 test
....
t2: byte-wise SSN armv8_x32 test
..
t3: memcpy pseudo random pattern test
....................................................................
t4: IRAM_to_DDRv1 test
...

t5: IRAM_to_DDRv2 test

Success: DDR Stress test completed!!!

Best regards,

Tim