i.MX8M Mini support mipi-csi raw12 issue

[tcchoub]

Dear Sir,

Our sensor is [AR0135] + [1280 x 960] + [2 mipi lane with 800 Mpbs each lane]

Cureently, we meet the following issues when we want to capture mipi-csi aw12 on i.MX8M Mini.

(A). Reference from NXP community:

[i.MX8M Mini] => imx8m mini mipi csi采图异常  => No success to capture raw10

[i.MX8M] => Confirmed support for RAW12 through 4-lane CSI-2 sensor on i.MX8M?  => Success to Capture raw12

(B). The case which we capture video image with "multiple sensor images"(分屏)

#modify "fsl-imx8mm-evk.dts"
data-lanes = <2>;
csis-hs-settle = <17>;
csis-clk-settle = <0>;

#modify "mxc_mipi_csi.c"
{
.code = MEDIA_BUS_FMT_SBGGR12_1X12,
.fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW12,
.data_alignment = 16,
},

#modify "mx6s_capture.c"
{
.name = "RAWRGB12 (SBGGR12)",
.fourcc = V4L2_PIX_FMT_SBGGR12,
.pixelformat = V4L2_PIX_FMT_SBGGR12,
.mbus_code = MEDIA_BUS_FMT_SBGGR12_1X12,
.bpp = 2,
},

...................................................

...................................................

case V4L2_PIX_FMT_YUV32:
case V4L2_PIX_FMT_SBGGR8:
case V4L2_PIX_FMT_SBGGR12:
width = pix->width;
break;

@@Then, We get the image below:

However, if we modify "mx6s_capture.c"
{
.name = "RAWRGB12 (SBGGR12)",
.fourcc = V4L2_PIX_FMT_SBGGR12,
.pixelformat = V4L2_PIX_FMT_SBGGR12,
.mbus_code = MEDIA_BUS_FMT_SBGGR12_1X12,
.bpp = 1,
},

@@We get the image below:

(C).The case which we capture video image with with heavily noise:

#modify "fsl-imx8mm-evk.dts"
&csi1_bridge {
fsl,mipi-mode;
fsl,two-8bit-sensor-mode;
status = "okay";
.......................................
};

#modify "mx6s_capture.c"
case V4L2_PIX_FMT_SBGGR12://RAW12
cr18 |= BIT_MIPI_DATA_FORMAT_RAW12;
break;

@@We get the image below:

(D). RAW12 Capturer and Player

We use "yavta" to capture raw12 video from our board
#yavta -c100 -p -fSBGGR12 -s 1280x960 -F/home/root/output.raw /dev/video0

And, uisng ffplay to play raw12 video in PC.
#ffplay.exe -video_size 1280x960 -pixel_format bayer_bggr16be output.raw

(E). Our Question:

(1). As we know, i.MX8M is different from i,MX7D, but i.MX8M-Mini is the same as imx7D. So, we want to know whether the configuration between i.MX8M and i.MX8M-Mini is the same ? When we set configuration as (C) (fsl,two-8bit-sensor-mode + BIT_MIPI_DATA_FORMAT_RAW12), the result seems more negative with heavily noise.

(2). How to solve "multiple sensor images"(分屏) in (B) ? It may be happened in i.MX8M Mini, not in i.MX8M.

(3). Do you have suggestion which tool can capture raw12 video ? And, which tool can play raw12 video in PC ?

Thanks a lot for your help.

Sincerely,

TC.Chou

[weidong_sun]

Hello TC,

Below is feedback from i.mx expert team:

------------------

For 1, the MIPI CSI2 modules are different between iMX8MM and iMX8MQ, but the CSI bridges are same.

For 2, you need check the frame width setting and camera resolution, another thing should be checked is the preview software.

For 3, nxp has the application  note AN12060 "Software ISP Application Note" which can be used to handle the RAW images on board, you can find it from nxp.com.

-------------------

Hope above answers can help you.

Have a ncie day!

B.R,

Weidong

[tcchoub]

Hello Weidong,

For 2, 

In mipi-csi frame size, we modify "mxc_mipi_csi.c":
val = mf->width | (mf->height << 16);
mipi_csis_write(state, MIPI_CSIS_ISPRESOL_CH0, val);

After I print "mf->width" and "mf->height", it's 1280x960.

In Camera, we output 1280x960 resolution.

Therefore,  they are the same.

Besides, because gstreamer can't support RAW12 video, we use yavta on .i.MX8MM board and ffplay(ffmpeg) it on PC.

#yavta -c100 -p -fSBGGR12 -s 1280x960 -F/home/root/output.raw /dev/video0

#ffplay.exe -video_size 1280x960 -pixel_format bayer_bggr16be output.raw

For 3, 

AN12060 "Software ISP" seems not support i.MX8MM

Our Question:

(A). Does "MIPI Serial clock Frequency" mean MIPI data rate for "each lane" or "total lane" (See the following table) ?

(B).  1280x960x30(fps)x12(bit) = 442,368,000 = 450Mbps. But, MIPI-CSI is dual-edge. So, we need 225(450/2) MHz. Is it correct ?

MIPI Serial clock Frequency (MHz)	HSSETTLE[7:0]	CLKSETTLECTL[1:0]
,1500	33	0
1490~1450	32	0
1440~1410	31	0
1400~1360	30	0
1350~1320	29	0
1310~1270	28	0
1260~1230	27	0
1220~1180	26	0
1170~1130	25	0
1120~1090	24	0
1080~1040	23	0
1030~1000	22	0
990~950	21	0
940~910	20	0
900~860	19	0
850~820	18	0
810~770	17	0
760~730	16	0
720~680	15	0
670~640	14	0
630~590	13	0
580~550	12	0
540~500	11	0
490~460	10	0
450~410	9	0
400~370	8	0
360~320	7	0
310~280	6	0
270~230	5	0
220~190	4	0
180~140	3	0
130~100	2	0
90~80	1	0

Thanks a lot for your help.

Sincerely,

TC.Chou 

[weidong_sun]

Hello TC,

See below,  please!
--------------------

For Q(A), each lane. it is the MIPI clock lane frequency * 2.

For Q(B), it is wrong, the calculation should include blank timing, so it should be: pixel clock frequency * bpp / lanes.

--------------------

Hope i.MX Expert's answers can help you!

Have a nice day!

B.R,

Weidong