To check out the possibilities for SSC on the MIPI DSI D-PHY, I need access to the MIPI D-PHY Registers of the i.MX8M-Mini (MIPI_DPHY_M_PLLCTL).
In the reference manual of the i.MX8M-Mini (IMX8MMRM, Rev. 2, 08/2019), in chapter 13.6.10, a MIPI PHY Memory Map/Register Definition could be found, with absolute addresses of 0x0 to 0x20.
These registers seem not to be mapped in the linear address space of the ARM.
I did not found any information about the access method (index, offset, …).
Does anybody have found additional information about MIPI D-PHY Registers access?
MIPI DSI D-PHY is controlled by MIPI DSI master and you can see block diagram in 220.127.116.11.2.So in 18.104.22.168.1 MIPI_DSI Memory map MIPI_DSI base address: 32E1_0000h
The needed Master PLL Control Register of the MIPI DSI D-PHY (MIPI_DPHY_M_PLLCTL) seems not to be in the MIPI DSI register space.
The register named MIPI_DPHY_M_PLLCTL is a 64 bit one. See Reference Manual 22.214.171.124.
The given address for the access does not make sense to me.
In the meantime, I got information about the MIPI DSI D-PHY register from NXP support.
(The information about the mapping of the registers in the reference manual is wrong and incomplete.)
The base address is 0x32E2_8000.
GPR_MIPI_M_PLLPMS 0x0c R/W
GPR_MIPI_M_PLLCTL_LOW 0x10 R/W
GPR_MIPI_M_PLLCTL_HIGH 0x14 R/W
GPR_MIPI_B_DPHYCTL_LOW 0x18 R/W
GPR_MIPI_B_DPHYCTL_HIGH 0x1c R/W
GPR_MIPI_M_DPHYCTL_LOW 0x20 R/W
GPR_MIPI_M_DPHYCTL_HIGH 0x24 R/W
GPR_MIPI_S_DPHYCTL_LOW 0x28 R/W
GPR_MIPI_S_DPHYCTL_HIGH 0x2c R/W
In my case, it did not help, because the MIPI D-PHY PLL is not active, as I noticed.