i.MX8M Mini EMI issue with SDIO to WLAN module

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i.MX8M Mini EMI issue with SDIO to WLAN module

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Contributor I

Hi All, 

We are using the Mini processor with a BCM43455 based wireless module and we have problems with the EMI emision.

The base frequency is 50MHz the drive strength is already set to the lowest possible. The communication is 3.3V level. 

We tried several PCB routing, decoupling and filtering tricks on the clock line already with just partial success. The routing length between the CPU and the module is about 50mm long.

The problem is that there are 50MHz multiplied peaks in the 550MHz to 1Ghz range which are above the EMI certification tresholds. 

Could somebody recommend effective EMI suppression ideas, which we can try, or is there any option in hte i.MX8M Mini, which can be tweaked so we could reduce the emission?

Thanks! 

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NXP TechSupport
NXP TechSupport

Hello Peter,

1. Some information to be confirmed
--Can your WIFI work normally?
--Have you noticed and corrected the 3.3V IO problem of i.MX8MM?

if not, see schematic of imx8mm-evk base board, page 13, please!

pastedImage_1.png
--Can you confirm that 50MHz multiplied peaks occur on the SDIO signal line?

2. On EMI of SDIO signals

For SDIO signals, simple filter below can improve EMI performance:

pastedImage_3.png

Just for your reference.

Hope the information is helpful for you.

Have a nice day!

B.R,

Weidong

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Contributor I

Hi Weidong,

We tried to add 22pF between CLK and GND. Also we have the series resistor in the design. Actually the best result we found was a 39.2ohm series resistor and 26.7pF capacitor close to the wireless module connector. 

Also we tried different ferrite beads on the CLK line in the position of the 39.2ohm resistor. Unfortulately none of them increased the performance enough.

Kind regards,

Peter Reitli

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NXP TechSupport
NXP TechSupport

OK, good job!

This shows that the filter circuit composed of 39.2ohm resistor and 26.7pF capacitor is suitable for your design.

B.R,

weidong

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NXP Employee
NXP Employee

Hi Weidong,

The 50MHz multiplied peaks happen on SDIO CLK signal.

Drive strength was already set to the minimum. And this acts as a resistor in series in the Pad itself.

Maybe adjusting the slew rate would help as well.

best regards,

Rod

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NXP TechSupport
NXP TechSupport

Hello Rod,

    Could you try to add 22pF capacitor between CLK line and GND?

    I feel that it should improve the quality of clock.

Have a nice day!

B.R,

Weidong

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