Most are aware of the DDRx timing constraints and PCB+package bondwire implications. Those lengths are in Table 27 of teh design guide. What about for other high speed signals?
I intend to use the FlexSPI in Octal mode to an FPGA. The DDR transfer mode is at 166MHz (max). The timing looks quite tight.
Can NXP provide package bond wire length for all pins? DDR, FlexSPI, and beyond? Xilinx provides this for all pins, all current devices.
In particular, I am using the MIMX8MM3CVTKZAA.
Stay safe,
Dennis