Hello,
For our design we are considering brownout condition where voltage on PMIC input drops below UVLO before the complete power down sequence is completed.
For the shutdown part, this seems to be OK based on Table 18 which shows they all just need to be disabled at the same time.
However, if the PMIC input voltage comes back quickly, the power up sequence may start before all rails have discharged to 0V. Does this violate the datasheet? Do I need to add a delay to the PMIC enable to allow for all rails to fully discharge? If so, to what voltage?
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Hi Kevin
>power up sequence may start before all rails have discharged to 0V.
>Does this violate the datasheet?
yes violate.
>Do I need to add a delay to the PMIC enable to allow for all rails to fully discharge?
yes
>If so, to what voltage?
as estimation one can consider "VIL" from Table 21. GPIO DC parameters
i.MX 8M Mini Applications Processor Datasheet for Consumer Products
Best regards
igor
Hi Kevin
>power up sequence may start before all rails have discharged to 0V.
>Does this violate the datasheet?
yes violate.
>Do I need to add a delay to the PMIC enable to allow for all rails to fully discharge?
yes
>If so, to what voltage?
as estimation one can consider "VIL" from Table 21. GPIO DC parameters
i.MX 8M Mini Applications Processor Datasheet for Consumer Products
Best regards
igor