i.MX8M DRAM training fails sometimes

[christian_mauderer]

Hello,

we have a custom design based on i.MX8MQ. After a change in the power supply, we now have a slightly increased rate of boards in the production that have problems with the DRAM training. To analyze the problem, we enabled debug messages in the U-Boot SPL. Now I get some magic numbers from the DDR training sequence but I haven't yet found documentation what the DDR training firmware wants to say with these. Does someone have an idea what the reason for such an behavior is or can someone point me to documentation that describes the i.MX8M DDR training sequence in more details? Especially: Is there some documentation for the PMU messages?

Output of a non-working start:

[TRACE] spl_dram_init() starting
DDRINFO: start DRAM init
DDRINFO: cfg clk
DDRINFO: ddrc config start
DDRINFO: ddrc config done
DDRINFO:ddrphy config start
DRAM PHY training for 1600MTS
check ddr_pmu_train_imem code
check ddr_pmu_train_imem code pass
check ddr4_pmu_train_dmem code
check ddr_pmu_train_dmem code pass
[PMU Major message = 0x0000000d]
[PMU Major message = 0x00000000]
[PMU Major message = 0x00000002]
[PMU Major message = 0x00000001]
[PMU Major message = 0x0000000a]
[PMU Major message = 0x000000fd]
[PMU Major message = 0x000000fe]
[PMU Major message = 0x00000008]
PMU String index = 0x00170003
arg[0] = 0x00000000
arg[1] = 0x00000003
arg[2] = 0x00000005
[PMU Major message = 0x00000008]
PMU String index = 0x04020000
[PMU Major message = 0x000000ff]
Training FAILED

And of a start where everything works as expected:

[TRACE] spl_dram_init() starting
DDRINFO: start DRAM init
DDRINFO: cfg clk
DDRINFO: ddrc config start
DDRINFO: ddrc config done
DDRINFO:ddrphy config start
DRAM PHY training for 1600MTS
check ddr_pmu_train_imem code
check ddr_pmu_train_imem code pass
check ddr4_pmu_train_dmem code
check ddr_pmu_train_dmem code pass
[PMU Major message = 0x0000000d]
[PMU Major message = 0x00000000]
[PMU Major message = 0x00000002]
[PMU Major message = 0x00000001]
[PMU Major message = 0x0000000a]
[PMU Major message = 0x000000fd]
[PMU Major message = 0x000000fe]
[PMU Major message = 0x00000004]
[PMU Major message = 0x00000003]
[PMU Major message = 0x00000009]
[PMU Major message = 0x00000007]
Training PASS
DRAM PHY training for 400MTS
check ddr_pmu_train_imem code
check ddr_pmu_train_imem code pass
check ddr4_pmu_train_dmem code
check ddr_pmu_train_dmem code pass
[PMU Major message = 0x0000000d]
[PMU Major message = 0x00000000]
[PMU Major message = 0x00000002]
[PMU Major message = 0x00000001]
[PMU Major message = 0x000000fd]
[PMU Major message = 0x000000fe]
[PMU Major message = 0x00000004]
[PMU Major message = 0x00000003]
[PMU Major message = 0x00000009]
[PMU Major message = 0x00000007]
Training PASS
DRAM PHY training for 1600MTS
check ddr_pmu_train_imem code
check ddr_pmu_train_imem code pass
check ddr4_pmu_train_dmem code
check ddr_pmu_train_dmem code pass
[PMU Major message = 0x00000000]
[PMU Major message = 0x00000005]
[PMU Major message = 0x00000005]
[PMU Major message = 0x00000006]
[PMU Major message = 0x00000006]
[PMU Major message = 0x00000007]
Training PASS
DDRINFO: ddrphy config done
DDRINFO:ddrphy calibration done
DDRINFO: ddrmix config done

With kind regards

Christian Mauderer

[jming]

Hi,

Please let me know , how this issue was resolved.

[christian_mauderer]

Hello @jming,

we originally have adapted the ATxImpedance, ODTImpedance and TxImpedance a bit to save some energy. We reverted the adaption to the default values recommended by NXP. This reduced the failure rate to an acceptable amount (also still higher than the original one).

Our current assumption is that a new batch of the processor had slightly different characteristics. It's also possible that something in the PCB production has changed. But that was at least partially from the same batch.

With best regards

Christian

[jming]

Hi @christian_mauderer ,

Grateful for your reply, thanks.