i.MX8DX DDR3L compliance

[nelson_loja_ext]

janspurek‌

Hello Jan,

1) What was the setup that NXP used to validate the design of DDR3L / LPDDR4 with i.MX8 I mean what did you used to have read burst and write burst on the RAM channel ?

2) Was it with this DDR stress tool, or something else?

3) Did you capture the electrical signals with an oscilloscope or a data analyser ?

4) Did you used an interposer for the probes? Did you used S-Parameters

5) Please describe me all your DDR compliance validation setup.

[jamesbone]

Hello  Nelson,

From your question,  I understand that you maybe one of our Aplha or Beta customer for the i.MX8X family devices, but unfortunately since they are not release yet, we cannot discuss details about the device since it is subject to changes, please contact by email  Jan Spurek or your local FAE, to get the answers about the i.MX8X since at the moment all information it is under NDA.

I apologize for this inconvenience.

Best Regards,

TIC Support Team