i.MX8 spi supports DDRx8 ?

cancel
Showing results for 
Search instead for 
Did you mean: 

i.MX8 spi supports DDRx8 ?

184 Views
Contributor III

Hi Sir,

I want to check flexspi bus have verified the DDRx8 mode . My customer will use Micron flash memory "MT35XU02G" and it work on the DDRx8 mode .

I found that the selected spi nor is already implement by the newer bsp (5.4.xx). Customer want to know imx8 flexspi can bring up from on the DDRx8 mode ?

We need upgrade SCU version to follow new bsp ?

https://source.codeaurora.org/external/imx/uboot-imx/commit/?h=imx_v2020.04_5.4.24_2.1.0&id=9454fee4...

/u-boot-imx/1_2020.04-r0/git/drivers/mtd/spi$ vim spi-nor-ids.c

#ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */
/* Micron */
{ INFO("n25q016a", 0x20bb15, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_QUAD_READ) },
{ INFO("n25q032", 0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
{ INFO("n25q032a", 0x20bb16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
{ INFO("n25q064", 0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
{ INFO("n25q064a", 0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
{ INFO("n25q128a11", 0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
{ INFO("n25q128a13", 0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
{ INFO6("mt25ql256a", 0x20ba19, 0x104400, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | USE_FSR) },
{ INFO("n25q256a", 0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_FSR) },
{ INFO6("mt25qu256a", 0x20bb19, 0x104400, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | USE_FSR) },
{ INFO("n25q256ax1", 0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | USE_FSR) },
{ INFO6("mt25qu512a", 0x20bb20, 0x104400, 64 * 1024, 1024,
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES |
USE_FSR) },
{ INFO("n25q512a", 0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
{ INFO6("mt25ql512a", 0x20ba20, 0x104400, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
{ INFO("n25q512ax3", 0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
{ INFO("n25q00", 0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
{ INFO("n25q00a", 0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
{ INFO("mt25qu02g", 0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
{ INFO("mt35xu512aba", 0x2c5b1a, 0, 128 * 1024, 512, USE_FSR | SPI_NOR_4B_OPCODES) },
{ INFO("mt35xu02g", 0x2c5b1c, 0, 128 * 1024, 2048, USE_FSR | SPI_NOR_4B_OPCODES) },
#endif

0 Kudos
2 Replies

154 Views
NXP TechSupport
NXP TechSupport

Yes, the i.MX8 processor supports the Double Data Rate (DDR) transfer on x8 data bus during boot based on the Configuration Parameters table read from the SPI Flash header at the early boot stage. All this is performed under the Boot ROM code control.

Regarding the System Control Firmware (SCFW), you have to always use the SCFW package, provided as the part of a particular BSP release.

Best Regards,
Artur

0 Kudos

141 Views
Contributor III

My Customer want to know Imx8qxp boot rom can support spi-nor that only work Octal SPI DDR x8 mode (MT35XU02GCBA2G12) ?
If yes , I think U-Boot does not support this mode and require modifying the code . Can you apply u-boot patch to me ?

SF: unrecognized JEDEC id bytes: 0f, 0f, 0f

Failed to initialize SPI flash at 0:0 (error -2)

 

 

 

0 Kudos